Component-level IP

[sakkiser]

Hello

I have a project with myRIO as target device. I added a component-level IP with simple vhdl code. I can see this component in my project explorer but when I drag the inputs and outputs of the component to my block diagram, he doesn't recognise them and says they are of type void when i want to link them. The same thing happens for all the other connectors and I/O onboard. When I drag LED0 for instance from my project exlporer to my blockdiagram it says it is void and I can't use it

. I can use the myRIO pallette in the blockdiagram to get to the LEDs and I/O but not for my Component-level IP. How can I solve this?

I also tried to use the hdl interface node but I can't find this on my pallette. I have installed labview, Real time, FPFA, the drivers and the compile tools.

 

greetings

[sakkiser]

It is fixed, just had to make a new VI under the target.

compiling problem: error 8

I turned my antivirus off and unchecked the search fast, are there any other possibilities that could generate this error that i could forgot?