Compiling a VI to a Virtual FPGA Target

[Amr95]

Is it possible to compile a VI to a virtual FPGA Target or do I have to have the real hardware? If it's possible I would be thankful for any tips for how to do it.

I'm not sure if a background about my program is needed to answer that question but in case it is, you could tell me and I would be glad to share the idea of my program with you.

[GerdW]

Hi Amr,

you can compile the FPGA VI even without attaching real hardware to your computer.

You just need to create a suitable target in your LabVIEW project…

[Amr95]

I tried doing that but somehow it didn't work. when I try to compile the FPGA target I get an error that my VI is broken. 

I am not sure if my words correspond to what I want to do, so I will describe what I want to do in details: I have a program that I did without using the FPGA module, the program is used to give me a sinus signal with a certain frequency and now I want to read this Sinus signal with a much lower frequency, so I figured that using the FIFO nodes is the way to do it and now as I want to convert my program under the FPGA Virtual target to be able to use the FIFO nodes, I get an error that my VI is broken and the compilation process gets interrupted. I am not sure what I am doing wrong, you said I should choose a suitable target, how could I know the target I chose is suitable?

I am still starting with the FPGA topic so I don't have much experience with it.

[GerdW]

Hi Amr,

@Amr95 wrote:

I have a program that I did without using the FPGA module, the program is used to give me a sinus signal with a certain frequency and now I want to read this Sinus signal with a much lower frequency, so I figured that using the FIFO nodes is the way to do it and now as I want to convert my program under the FPGA Virtual target to be able to use the FIFO nodes,

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So your VI is not broken, when you run it under the "My computer" target?

And it gets broken, when you move it into the "FPGA" target?

Then it contains functions not available in the FPGA…

On the other hand: Why do you want to move it into the FPGA target just to use some FIFOs?

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@Amr95 wrote:

 I am not sure what I am doing wrong,

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You didn't attach your VI.

[Amr95]

Yes it only gets broken when I move to the FPGA target.

According to the FPGA National Instruments online course I need to have my VI under the FPGA target, in order to use the FIFO nodes, correct me if I am wrong. 

I added my VI, I didn't add it first because I thought the problem was in my choices for the compiling properties but apparently there are other problems.

[GerdW]

Hi Amr,

please downconvert your VI to LV2017…

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@Amr95 wrote:

Yes it only gets broken when I move to the FPGA target.
According to the FPGA National Instruments online course I need to have my VI under the FPGA target, in order to use the FIFO nodes, correct me if I am wrong.

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The tutorials surely also mentions the limited set of functions available in the FPGA.

You still need to explain why you need FIFOs at all!

[Amr95]

I downgraded it to 2017 and uploaded the SubVIs as well, DF-Block is the main VI.

As I said I want to have two loops one writing a sinus signal and one for reading a sinus signal with a certain sampling rate to determine what is the lowest frequency possible that I could set to get a sinus signal looking similar to the original one but with less data points. After seeing the tutorials and according to the instructions of my boss I should be going the FPGA way. I am doing part of a project for a dialysis machine which is based on FPGA and that's why I think I should use FPGA in this program. I may have some misconceptions and I would be glad if you point them out to me, thanks in advance 🙂

EDIT: you could see in my program that I tried to implement the sampling rate part but it didn't work, as you could see the frequency stays the same even though the loops are working with different time rates that's why I assumed using the FIFOs would bring me further.

[GerdW · Accepted solution]

Hi Amr,

as I expected before: your VI contains functions not available in the FPGA target.

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@Amr95 wrote:

After seeing the tutorials and according to the instructions of my boss I should be going the FPGA way. I am doing part of a project for a dialysis machine which is based on FPGA and that's why I think I should use FPGA in this program.

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I don't see any FIFOs in your VIs.

I don't think you need to "go the FPGA way" right now.

Again: why do you think you need the FPGA right now to run your VI(s)?

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@Amr95 wrote:

I may have some misconceptions and I would be glad if you point them out to me, thanks in advance 🙂

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There are:

• Using ExpressVIs not accessible for the FPGA target.
• Using wrong datatypes for FPGA target VIs.
• Using silly (aka Rube-Goldberg) while loops in your main VI.
• Not cleaning up the block diagram.
• Much more…

Suggestion:

1. Rethink your overall system design - together with you boss.
2. Do some more LabVIEW tutorials, start with Core1 and Core2.
3. Do even more LabVIEW tutorials, including Realtime1, Realtime2 and FPGA.
4. Think about system design for medical equipment before starting to implement any code…

[Amr95]

Thanks for the feedback, I appreciate it! 
It would be nice to let me know what you mean by cleaning up the block diagram. Do you mean the clean up diagram button by that?

[Amr95]

You mentioned that the functions in my program are not supported by the FPGA Target. Isn't the meaning of compilation is to translate the program into an executable code by the FPGA Target? I replaced the express VIs with other Functions that should be supported by the FPGA Target but I assume that the rest of data should translated to an executable data forms by the FPGA Target when I try to compile the code.