Compilation Stuck at Placing and Routing

[anzarc]

Would really appreciate help with an issue I have.

I am using a cRIO-9074 and programming it with LabVIEW 2015. Now that I have started to add more code onto the FPGA, the compilation just hangs at "Placing and Routing". I have let it run overnight to come back in the morning to see the time elapsed is over 10 hours. The operating system is Windows 7 with an i5 processor. Any help will be appreciated.

Thanks,

[Oligarlicky]

That usually happens when your design is on the border of being able to fit in your FPGA. You'll benefit from optimizing your design or buying a bigger FPGA.

[christian_w]

use NI update service to check for the latest updates

[GerdW]

Hi anzarc,

which OS are you using?

I hade the same problem on a Win7-32bit-OS with 4GB RAM: this wasn't enough for the Xilinx compiler.

After changing to a computer with Win7-64bit-OS (and 8GB RAM) all runs well.

You can also use the compile farm service from NI! (You do have a SSP, don't you?)

[anzarc]

I am actually pretty new to LabVIEW and FPGA. How would you check if your design is getting too large for your FPGA system?

[GerdW]

Hi anzarc,

before the "placing and routing" step you get estimations on resource usage…

[psystein]

you either wait for the compliation to return a error or Analyse the results of the Estimated Resource Usage. 

In the ERU Results if your code uses more than 99% of slice LUT, then the compilation will not succeed.

Am pretty sure that its the code needs to be optimized, i have used the compiler with many Windows OS and with 4gb RAM too, it takes time but go through.

[Sam_Sharp]

As the others have stated - optimising your code is by far the best way to - if you google for 'Advanced FPGA Throughput' I think there's a PDF that goes into detail about how to optimise FPGA code to reduce resource usage etc.

There is a way to significantly reduce FPGA compile times though if you have a fairly modern CPU: http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297

[anzarc]

Thanks for the answers.

The pre-syntiesis estimation shows the slice LUTs at 57%, but after the synthesis step, it jumps to 87%. I see how 99% is high, but should it be giving me problems at 87%?

Thanks again for the help!