Change FPGA CLIP without recompilation

[FPGAsoCool]

Hi Everyone,

I have written several custom CLIPs for NI-6583 for different FPGA VIs. If I place all these FPGA VIs in the same project, I noticed that every time I swap CLIP, the FPGA VI needs to be recompiled (even though there aren't any changes to the CLIP or the VIs). 

Is there anyway to overcome this (besides creating multiple projects)? 

The custom CLIPs are pin-specific to different custom cables, so I can't just write one custom CLIP that works for all the FPGA VIs. 

Thank you in advance.

[rolfk · Accepted solution]

Is the front panel and FIFO etc, for the FPGA file exactly the same? If so you need to replace the Open FPGA VI Reference xnode with the Open Dynamic Bitfile Reference node, and determine the path of the correct bitfile programmatically.

The Open FPGA VI Reference xnode embeds the bitfile at compile time according to its configuration. So every time you change the bitfile (or VI to use) the VI containing the xnode needs to be recompiled.

[Terry_ALE]

Can you expand on what you mean by swapping the CLIP?  You remove it from the project, add another one, add to the FPGA VI?

[rolfk]

You create a separate target for each CLIP, and in there a separate bitfile on each.

The FPGA VI needs to have the same register and host FIFO interface. This means you need to have the same host FIFOs in each of these targets and use the same main FPGA VI front panel. The easiest is to use the same VI in each target and utilize the conditional compile structure on the diagram and in subVIs to access the variable IO from the CLIP. Then create a bitfile for each of them and last but not least you use one of those targets to create your realtime app in and create code to dynamically load the correct bitfile.

Disclosure: I haven't used R Series FPGA boards but only cRIO and sbRIO targets and in there it works this way. Not 100% sure you can create multiple targets for the same R Series FPGA hardware.

[Terry_ALE]

---

@rolfk wrote:

You create a separate target for each CLIP, and in there a separate bitfile on each.

The FPGA VI needs to have the same register and host FIFO interface. This means you need to have the same host FIFOs in each of these targets and use the same main FPGA VI front panel. The easiest is to use the same VI in each target and utilize the conditional compile structure on the diagram and in subVIs to access the variable IO from the CLIP. Then create a bitfile for each of them and last but not least you use one of those targets to create your realtime app in and create code to dynamically load the correct bitfile.

Disclosure: I haven't used R Series FPGA boards but only cRIO and sbRIO targets and in there it works this way. Not 100% sure you can create multiple targets for the same R Series FPGA hardware.

---

Never mind my question above.  I was forgetting that the CLIP is socketed in this case.

The above seems right.  You can create multiple targets for FlexRIO.

[FPGAsoCool]

Hi Rofl, your suggestion worked great! I've always referenced the FPGA VI instead of specific bitfiles, had no idea there were alternatives.

Learning something new everyday, thank you so much!

[FPGAsoCool]

Also, I think both Open FPGA VI Reference or Open Dynamic Bitfile will work. 

Open Dynamic Bitfile is more manual (requiring manual typing of FPGA target name, bit file address etc.) but gives a little more freedom.