Butterworth Filter on Labview FPGA

[Zouhair]

Hello,

I have a question about butterworth filter on labview FPGA. The VI does not function as I required (rising noise at low frequencies for a filtered signal (20kHz) with a 2nd order high-pass filter, with a cutoff frequency of 2kHz), the sample rate is of 20MS/s.

I just want to know how the Butterworth coefficients VI works, how does it generate the coefficients? because I would like to make some tests with my own coefficients, and for that I should associate the coeffcients generated with the classical ones (B and A in Matlab for instance).

PS : for a butterworth 2nd order high-pass filter, we have 6 scaled coefficents normally (Matlab or other programming laguages), but when I take a look at the coefficients generated by Labview for the same type of filter, there are 3.

Thank you in advance,

Zouhair

[JLewis]

Hi Zouhair,

The coefficients are produced by the Butterworth Coefficients VI on the FPGA Interface>>Scaling palette (available from VIs under My Computer). While the code there isn't available, it basically starts with the desktop floating-point Butterworth Coefficients.vi and scales those by 2^30 to fit into I32 integers. In cases where the cutoff frequency is very low relative to the sample rate (as in your case), there are some tricks done to improve the numerical behavior--these are coupled with the FPGA filter implementation, so . We only store 3 coefficients because the coefficients contain redundant information in the Butterworth structure.

The challenge in your case is that your sample rate is extremely high relative to the signal frequency, which is making the problem basically intractable with fixed-point math. The simplest solution (if practical) would be to reduce your sample rate to somewhere in the neighborhood of 10x the signal frequency, and you should see much better filtering behavior.

If you really need to sample at the higher rate, the Rational Resampler allows you to reduce the sample rate without aliasing higher frequency noise into your signal.

If none of that is practical, it sounds like you'll need to go to floating-point math, using SGL precision and roll your own filter.

[Zouhair]

Hi ,

Thank you for your answer, it was really helpful.

However, since I can't reduce my sample rate (digitized signal at 20MHz), and that the Rational Resampler is not very performant for a sample rate of 20MS/s (maximum Input Sample Rate of 6 or 7 MS/s, with the minimum stopband attenuation), it seems like I will have to create my own filter, or not use a high-pass filter in the 20MHz loop.

Zouhair

[JLewis]

One more option I should mention is the Digital Filter Design Toolkit, which contains a richer set of features, including resampling filters designed to work at higher sample rates (ie, in a single-cycle timed loop). I'm not sure if this will have everything you need, but it might be worth an evaluation.

[AshwiniWini]

Hi,

Information given by you is very helpful. Thank you.

I am trying to implement 8th order filter on FPGA, Can you please recommend if is there any way i can do it? Do you know any 3rd party library which already does that.

Mainly, Can FPGA support 8th order filtering? because default vi present on FPGA panel only support max 4th order.

Any suggestion would be very helpful.