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Build array into timed cycle loop FPGA

Hi, I'd like to acquire four digital signals with MyRIO fpga when i click an "acquire" button and put them in four arrays of 500 elements each. I made this:

image001.png

 

but I receive these errors:

Immagine2.pngImmagine.png

 

Immagine3.png

I have defined fixed arrays at the start of the cycle. What is the problem?

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Message 1 of 16
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use an indexer/counter to put the data into your array .... append will not work

Message 2 of 16
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Hi andrea,

 

I have defined fixed arrays at the start of the cycle. What is the problem?

You (want to) add new elements to a fixed-sized array. That is the problem!

 

As said before: replace elements in your array(s)…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
Message 3 of 16
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Thanks guys. Is this a good way to acquire a digital signal? Are there better ways/express VI to do this basic task?

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Message 4 of 16
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When using replace instead of build array this way is ok, but it really depends on what you do with the data afterwards. Do you need to convert each bit to a I16 (throwing away 15 bits of the I16)? That will consume a lot of resources, 4 arrays of 500 I16 elements each. What do you do with the I16 arrays afterwards?

 

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Message 5 of 16
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First, I want to show these bit as zeros and ones, not with LED. I know this is a bad way to do because I waste 15 bit!

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Message 6 of 16
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Show where? On the front panel of the FPGA VI?

 

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Message 7 of 16
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yes

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Message 8 of 16
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Well then this looks like a test application anyway, in that case I would not worry about inefficiency as long as the code fits on the FPGA.

 

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Message 9 of 16
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An FPGA does not have a front panel.  When you compile an FPGA, you are difining actual gates on the FPGA.  There is no display once it is deployed.  What you want to do is put these values into a DMA FIFO to pass the data up to the Real Time program.  You can technically show that front panel.  So your FPGA should just read these digital lines and put them in the FIFO.  No need for arrays in the FPGA.  The RT code can then build arrays, if you really want to do that.  But it is still better if you predefine your array and then replace elements as you go (a lot more efficient for the memory).


GCentral
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Message 10 of 16
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