Build array into timed cycle loop FPGA

[dan_u]

Well for quick debugging I find it quite useful and simple to be able to show some values on the (inexistent?) FPGA VI front panel. I know that behind the scene the compiled code is deployed and there's some data transfer implemented to show it on the front panel of the FPGA VI which is open on the host PC, but I like the fact that NI takes care of that. No need to implement DMA or anything just for quick debugging.

[Hooovahh]

I'm a fan of this quick and dirty testing of FPGA code.  I mentioned that I did this to someone at NI and they looked at me like I had a cat on my head.  They asked why I would want to do that since the front panel only updates once every couple milliseconds at best.  I explained that for debugging and showing the latest value, it was super convenient.  Also having controls like a button that forces states of a state machine, or an indicator for debugging, is useful.

EDIT:  And yeah for the OP, FPGA must have fixed array sizes, the build array makes the array size grow and the FPGA can't have that.  Initialize the array with the number of elements you want, then do a replace keeping track of the pointer of the last write.

[crossrulz]

Yeah, but 2013 has some AWESOME simulation schemes now that make all of that debugging very easy. And it all works inside of LabVIEW. Seriously, go look up the Desktop Simulation Node.

[Hooovahh]

I know it exists and I've been meaning to try it but it can't be easier than just running a vi.

[crossrulz]

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@Hooovahh wrote:
I know it exists and I've been meaning to try it but it can't be easier than just running a vi.

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Once you got it set up, it's better.  You have cycle accuracy for your inputs/outputs and you can still get/recieve data via your normal DMA and front panel connections.

[dan_u]

Yes, but sometimes you need some debugging with real hardware connected. That's when the FP controls can be very useful.

Otherwise I agree the simulation mode is more convenient (also saves a lot of time since there's no need to compile the FPGA VI).