Boolean value control

[zyb1003]

Hi everyone, 

Now I have arctan function in a single cycle time loop in my fpga VI. I want the 'input valid' to be false for the first cycle, and to be true for the second cycle, then to be true again every 4 cycles.

What's more, in the host VI, it has a update button, I want the action of update button synchronize with the input valid input value. 

I hope I can get answers from you guys. 

Thank you. 

[ogk.nz]

That is pretty straightforward really, just use the iterations counter from the loop and some simple math.

Decrement, Quotient by 4, equal to 0.

You say synchronise? Do you just mean influence it? In that case simply put the control inside the loop.

[Terry_ALE]

I suggest using a counter based on a shift register.

Before this counter begins, check the iteration of the loop and start this only after the count is greater than 1.

When the count is greater than 1 start the shift register counter.  When it hits 4, send a true to the input valid and reset the counter.  This will repeat.

FYI, something is fishy about trying to 'sync' from a button on the host.  Host to Target latency is not deterministic.

Typically the input valid is driven from a preceding data source.  See this link from the LabVIEW FPGA 2016 help http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgaconcepts/fpga_handshaking/

[Terry_ALE]

Iterations value from the loop is an I32 and if this runs long enough it will hit maxint for I32 and no longer work.

[crossrulz]

Use a shift register to keep a count.  You can initialize it to 3.  So each iteration, you increment the value.  If the value is equal to 4, set it to 0 (use the Select function) and set your Valid to TRUE (simple since you already have the Equal to 4 will output the TRUE).

I am not understanding your host boolean button.  Is it to reset the counter?

[crossrulz]

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@ogk.nz wrote:

That is pretty straightforward really, just use the iterations counter from the loop and some simple math.

Decrement, Quotient by 4, equal to 0.

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In an FPGA, Quotient is very expensive.  In fact, it cannot even run in a SCTL.  And also the iteration counter will max out that I32 fairly quickly in an FPGA (I have done it many times).  Using the shift register and a Select to reset the counter is the more efficient method.

[ogk.nz]

Too early in the morning, I totally missed the FPGA bit. Also, any explanation on why quotient is hard on the FPGA?

[zyb1003]

What you said is absolutely right. 

Basically, in the FPGA VI, I have a input sine signal at 25MHZ, and the sample rate is 100MHZ, that is to say I get 4 points (Q,I,-Q,-I) per period. I want to calculate arctan(Q/I). 

In the host vi, the signal's amplitude and phase can be modulated, the update button is used to update signal. What I want to achieve is when the signal is updated, I can still get (Q,I,-Q,-I) in order and calculate arctan (Q/I). Otherwise, without synchronization, it might be arctan (I/-Q) or arctan(-Q/-I).

So you say the synchronization means clear the counter that seems make sense. 

[crossrulz]

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@ogk.nz wrote:

Also, any explanation on why quotient is hard on the FPGA?

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It just uses a lot of fabric and takes multiple cycles.  About 15 years ago I could give a better explanation.  But division is hard on micro-controllers too (comparatively to addition, subtraction, and multiplication)

[Terry_ALE]

I think division is computed as many successive subtract functions.