Boolean value control

[altenbach]

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@Terry_ALE wrote:

I think division is computed as many successive subtract functions.

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There are many different algorithms.

(And if implemented wrong in silico, you might even get buggy output. Remember the Pentium FDIV bug where the SRT algorithm had a few entries missing in the lookup table.:D)

[altenbach]

Of course if we are dealing with integer powers of two, there are plenty of ways to not use Q&R.

Here is one possibility (but there are plenty more!). 😄

(You can easily shift the "phase" by incrementing [i] by a small number.)

[zyb1003]

Hi crossrulz, 

Thanks for replying me about how to sample one point per 4 cycles. Now I still have question about how to synchronize the 'input valid' in the FPGA VI with update button in the host VI as I indicated above (IQ sampling). 

Thank you

[mterz]

Could you clarify what you want the functionality of the update button to do and what you mean by having that button synchronized to the input valid? I am not sure I fully understand what you are looking for.

Thanks!

[zyb1003]

Hello mterz,

The sample points are (I,Q,-I,-Q). The synchronization means each time I click the update button on the host side, for the arctan(y/x) function in FPGA side, y should always be I, x always be Q. The phase calculated should always varies within a short range. Otherwise, (y,x) might be (Q,-I) or (-I,-Q). 

Thank you. 

[Terry_ALE]

Where do the values come from?  Hardware inputs?  FIFO?

input valid should be true when there is valid data coming in

The latency from a button being pressed on the Host to when it is read in the FPGA is certainly going to keep things out of sync and will not guarantee that input valid and actual valid data are synchronized.