A general question regarding the resource usage of Block Ram primitives in LabVIEW FPGA.
I'm investigating utilising a group of BRAMs as "interconnects" between several different loops running on my FPGA. I can serialise and deserialise many values into these BRAMs so that the depth can be used more or less efficiently.
My question regards how (or whether) the attached feedback nodes are represented on Fabric. Are they purely place-holders so that the latency can be visualised or are they actually implemented in fabric (LUTs, REgisters, SRLs)?