02-07-2012 09:59 PM
Hi,
I have a problem with a simple FPGA Target VI (attached). I would like to have 1 analog input, 1 analog output and 1 digitial output controlled and monitored from the host application. When only the analog input routine is compiled and downloaded to the FPGA, everything works ok, but as soon as I add either a didital output or a analog output, the analog input returns 0 whatever the actual input signal. I've haven't attached the host VI, since the same happens when the Target VI is run interactivelly.
It doesn't get any simpler than this, but I can't figure out what's wrong with the VI.
Regards,
Lukas
02-09-2012 09:42 AM
Hi Lukas,
Looking at your VI, I notice you aren't using any loop timers to regulate your acquisition. What CompactRIO Modules are you using? I highly recommend looking at the LabVIEW FPGA shipping examples included in your software installation. There are examples for almost every Module located in the NI Example Finder (Help >> Find Examples...) under Toolkits and Modules >> FPGA >> CompactRIO >> Module Specific. Try a few of these examples out and let us know if you have any troubles.
Regards,
Alexander M
Applications Engineer
National Instruments
02-10-2012 01:25 PM
Hi Axlexander,
Sure I have looked at the examples, but adding or removing loop timers does not seem to help. In fact the "Analog Ouput - R Series.lvproj" does not even contain a timer. For the provided example I have removed the timers for..."simplicity" I guess.
I am using a PCI card by the way (PCI-7831R).
Regards,
Lukas
02-10-2012 01:29 PM - edited 02-10-2012 01:32 PM
Is there any possibility there's a wiring problem here, such that when you enable the output you're grounding the input? What's going on outside the FPGA in your system?
EDIT: by the way, you're fine with no timing mechanism on FPGA. On other platforms, all loops should have some sort of wait to avoid the condition where one loops runs as fast as possible and prevents any other loop from running. This condition doesn't occur in an FPGA.