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Analog Output Buffer Length and Update Rate
jw81
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03-03-2005 01:54 PM
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Is there a formula for buffer length and update rate? I am confused what is buffer length and update rate. I attached my VI below.
It is a data reader from a file and send two different voltages to two different channel.
It is a data reader from a file and send two different voltages to two different channel.
03-06-2005 10:31 PM
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Hi, is there anyone could help me? THanks
AnujD
NI Employee (retired)
03-07-2005 01:37 PM
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What kind of formula are you looking for?
Here's some information defining about analog output terms:
Number of Channels – The number of simultaneous analog signals that the product can generate.
Resolution – The number of bits that the digital-to-analog converter (DAC) uses to generate the analog signal. The higher the resolution, the higher the number of divisions the range is broken into, and therefore, the smaller the voltage step capable of being generated. Resolution is only one indication of DAQ product accuracy. You must consider at least the relative accuracy (linearity), offset errors, and gain errors to fully understand the accuracy of the DAQ product.
Common-Mode Isolation – The maximum allowable difference in voltage between the D/A converter channel and earth ground or another channel.
Max Update Rate – The fastest rate at which the analog output channels can convert digital data points to analog values. Some products can generate the analog output samples directly from a buffer of memory on the board and can therefore meet the max update rate under all conditions. Boards that have DMA data transfer capability can also meet the max update rate consistently because they have the DMA processor dedicated to transferring the data. Boards that require interrupt and programmed I/O transfers may not be able to consistently meet the max update rate because of the processor speed or other functions that the processor is trying to perform at the same time as transferring data to the analog outputs.
Type of DAC – Different applications require different types of digital-to-analog converters (DACs) for optimal performance. For example, an AC-class signal is best generated with a delta-sigma modulating DAC. Examples of common types of DACs are multiplying, double-buffered multiplying, and delta-sigma modulating.
FIFO (First-In-First-Out) Buffer Size – The FIFO is a block of memory used to store a certain number of samples on the board so that data can be continually generated, even when there are interrupt latencies preventing data transfers from PC memory. The FIFO size is specified in number of samples so that you knowhow many sample points can be buffered. The amount of latency that the product can tolerate is determined by multiplying the DAC conversion time (1/update rate) by the size of the FIFO.
Data Transfers – Data transfers are the methods available to transfer digital data from computer memory to the DAQ board. Options are DMA, interrupt, and programmed I/O. For programmed I/O transfers, the CPU in the PC writes data to the DAQ board whenever the CPU receives a software code to generate a single analog value. Interrupt data transfers occur by the DAQ board causing an interrupt to the CPU, telling the CPU to write the digital data to the DAQ board. DMA transfers use a DMA controller instead of the CPU to move digital data from computer memory onto the DAQ board. Even though high-speed data transfers can occur with interrupt and programmed I/O transfers, they require the use of the CPU to transfer data. DMA transfers are able to move data at high speeds and keep the CPU free for performing other tasks at the same time.
DMA Modes (only for boards with DMA transfer capability) – This specification tells the methods of DMA transfer available to transfer data from computer memory to the analog output circuitry on the DAQ board. Options for DMA modes are single and demand transfers. In single-transfer mode, one data value is transferred for each DMA request assertion, which is the slowest method of transfer because the DMA controller must arbitrate for the system bus with each transfer. Demand-transfer mode increases system throughput because the DMA controller performs several DMA transfers once the DMA controller has gained bus access. For demand-mode transfers, the DMA controller performs DMA transfers at the fastest possible rate as long as the DAQ board asserts its DMA request. When the DAQ board unasserts this DMA request, transfers are held off. For more information on DMA modes, see Application Note 011, DMA Fundamental on Various PC Platforms.
Here's some information defining about analog output terms:
Number of Channels – The number of simultaneous analog signals that the product can generate.
Resolution – The number of bits that the digital-to-analog converter (DAC) uses to generate the analog signal. The higher the resolution, the higher the number of divisions the range is broken into, and therefore, the smaller the voltage step capable of being generated. Resolution is only one indication of DAQ product accuracy. You must consider at least the relative accuracy (linearity), offset errors, and gain errors to fully understand the accuracy of the DAQ product.
Common-Mode Isolation – The maximum allowable difference in voltage between the D/A converter channel and earth ground or another channel.
Max Update Rate – The fastest rate at which the analog output channels can convert digital data points to analog values. Some products can generate the analog output samples directly from a buffer of memory on the board and can therefore meet the max update rate under all conditions. Boards that have DMA data transfer capability can also meet the max update rate consistently because they have the DMA processor dedicated to transferring the data. Boards that require interrupt and programmed I/O transfers may not be able to consistently meet the max update rate because of the processor speed or other functions that the processor is trying to perform at the same time as transferring data to the analog outputs.
Type of DAC – Different applications require different types of digital-to-analog converters (DACs) for optimal performance. For example, an AC-class signal is best generated with a delta-sigma modulating DAC. Examples of common types of DACs are multiplying, double-buffered multiplying, and delta-sigma modulating.
FIFO (First-In-First-Out) Buffer Size – The FIFO is a block of memory used to store a certain number of samples on the board so that data can be continually generated, even when there are interrupt latencies preventing data transfers from PC memory. The FIFO size is specified in number of samples so that you knowhow many sample points can be buffered. The amount of latency that the product can tolerate is determined by multiplying the DAC conversion time (1/update rate) by the size of the FIFO.
Data Transfers – Data transfers are the methods available to transfer digital data from computer memory to the DAQ board. Options are DMA, interrupt, and programmed I/O. For programmed I/O transfers, the CPU in the PC writes data to the DAQ board whenever the CPU receives a software code to generate a single analog value. Interrupt data transfers occur by the DAQ board causing an interrupt to the CPU, telling the CPU to write the digital data to the DAQ board. DMA transfers use a DMA controller instead of the CPU to move digital data from computer memory onto the DAQ board. Even though high-speed data transfers can occur with interrupt and programmed I/O transfers, they require the use of the CPU to transfer data. DMA transfers are able to move data at high speeds and keep the CPU free for performing other tasks at the same time.
DMA Modes (only for boards with DMA transfer capability) – This specification tells the methods of DMA transfer available to transfer data from computer memory to the analog output circuitry on the DAQ board. Options for DMA modes are single and demand transfers. In single-transfer mode, one data value is transferred for each DMA request assertion, which is the slowest method of transfer because the DMA controller must arbitrate for the system bus with each transfer. Demand-transfer mode increases system throughput because the DMA controller performs several DMA transfers once the DMA controller has gained bus access. For demand-mode transfers, the DMA controller performs DMA transfers at the fastest possible rate as long as the DAQ board asserts its DMA request. When the DAQ board unasserts this DMA request, transfers are held off. For more information on DMA modes, see Application Note 011, DMA Fundamental on Various PC Platforms.
03-07-2005 09:35 PM
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How can I relate Update Rate with frequency? Is there a formula? Thanks
Christian Lindenblatt
Member
03-08-2005 02:05 AM - edited 03-08-2005 02:05 AM
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I have had the same problem because this variant of NI is a little bit difficult to understand.
Yes, there is a formula!
The Frequency f_out is determined by the update rate and the sample rate.
f_out=f_upd/sample rate
The sample rate is equal to buffer length.
The internal clock of your Daq-Card for example 20MHz (consult the manual), which generates the update rate f_upd thereby is divided by an integer.
To generate a sine-frequency of 16kHz with 50 samples/oscillation an update rate of 800kHz is needed.
f_upd = 16000*50
For this reason the internal clock must be divided by 25.
20MHz/25=800kHz
Yes, there is a formula!
The Frequency f_out is determined by the update rate and the sample rate.
f_out=f_upd/sample rate
The sample rate is equal to buffer length.
The internal clock of your Daq-Card for example 20MHz (consult the manual), which generates the update rate f_upd thereby is divided by an integer.
To generate a sine-frequency of 16kHz with 50 samples/oscillation an update rate of 800kHz is needed.
f_upd = 16000*50
For this reason the internal clock must be divided by 25.
20MHz/25=800kHz
Message Edited by Christian Lindenblatt on 03-08-2005 02:06 AM
