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9870 fpga timeout issue

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I am collecting data from serial instrument(read only) , instrument uses 115200baud, 8 bits no parity 1 stop and no flow control none of which are configurable.

 

It usually works quite well but occasionally it will timeout on startup, examining the port properties it says there are 0 bytes available however the instrument is still sending bytes. Unplugging the serial cable and reconnecting gets it going again..But why ?

 

I do detect and recover happily from communication errors(framing etc), but I cannot get anything to recover from this particular instance of timeout except by physical intervention.

 

If I don't connect the instrument and startup (forcing a real timeout) and then connect the instrument it will always seems to startup happily.

At this stage I would "reset" the port on a timeout , but I cannot find a method/technique to do this.

 

This is a 9014 with 9114 chassis and a 9870 module (amongst others) and labview 11 sp1

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Eric416,

 

Your post indicates that this problem happens on 'startup'.  If that includes applying power to the cRIO, 9870 and the instrument then I would tend to suspect that one of the ports is latching up due to one port powering up before the other.  What kind of instrument are you connecting to?  You might try installing a serial isolator between the 9870 and the instrument and see if it makes a difference.

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When I say startup I also mean just running on the rio using labview, however the same does occur when powering up.

 

The instrument is a radar unit with serial output, we have line level converter to go from 3.3v to rs232, however we have had similar issues with counter with rs232 interface (no level conversion)

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Accepted by topic author Eric416

Eric416,

 

I've had a 9870 running in a cRIO-9074 (scan mode ) for some time now with no problems.  I think I would still try the isolator just to eliminate the posibility of hardware latchup.  Next I'd hang an oscope on the TX/RX and observe what kinds of things are happening on startup/powerup.  Have you tried having your code close and reopen the VISA session when the timeout occurs? 

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It is being used in FPGA mode, I will look into trying an isolatorto see if that solves the issue

 

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