5781 examples

[newFPGAuser]

Hello,

A few basic questions regarding using the 5781:

1. Where can I find this example:NI 5781 Wrapback.lvproj? Can somebody please upload it for me? It is not available in my LV 2017,2016 or 2015 folders.
2. The 5871 is called a transceiver, can somebody please explain where the mixer is implemented? It just seems only like a fast ADC/DAC. Does this mean I can send in an analog input and directly obtain I, Q signals as the output?

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[Case_in_Point · Accepted solution]

Hi newFPGAuser (nice name!),

I don't believe the Wrapback example project has come with the FlexRIO driver for a little while, I've never seen it before and looking into it most of the hits I'm finding are around 2009/2010. I'm assuming you saw it mentioned in the 5781 user guide - http://www.ni.com/pdf/manuals/372968a.pdf? If you're just interested in testing the 5781 and making sure the AI and AO work, you could definitely use the 5781 Getting Started example project; it does loopback as well and would be perfectly serviceable.

To the second, it's called a transceiver because it does both input and output (transmit and receive), not because it does any mixing itself. This specific FAM (FlexRIO Adapter Module) only works at baseband. Contrast with the 5791 FAM, which specifically works with RF signals and does include down/upconversion. The 5781 essentially just does differential analog input/output.

Cason

NI Applications Engineer

[newFPGAuser]

Hi Cason,

Thanks for the clarification. Yes, I was going off of the pdf you linked to. In the second example, i.e. the one with the block diagram, is it necessary to use a timed structure? Why not just use a while loop? I have (limited) experience with the 7851/52R and would like to know if this module+RIO combination requires the use of a timed loop? I presume that using a non-timed structure will automatically execute operations at the top level FPGA clock.

Apologies for butchering terminology, my name should tell you why! :)!

[Case_in_Point]

No worries about the simple questions, we all started there!

It's not technically necessary to use a timed while loop (also called a single cycle timed loop). However, they are almost ubiquitously used in FlexRIO programming for the specific purpose that they execute everything in the loop in a single clock cycle. If you didn't care how many clock cycles some code would take, you can certainly use a non-timed while loop. It will indeed execute actions on every clock tick of the default 40 MHz clock, however, the default logic is to basically take one clock cycle for each operation. So if you added two numbers, incremented, then did a logic comparison, even though all of that could very easily be condensed into one clock cycle in a timed loop, an un-timed loop will just take a clock cycle to execute each operation. There's also another 2 ticks of overhead to the While loop itself if I remember correctly; one to check the stop condition and one to actually move to the next iteration.

So basically you can certainly use untimed loops, they'll operate a good bit slower than a timed loop but obviously still much faster (and more reliably) than running code in a non-FPGA context.

Regards,

Cason

NI Applications Engineer

[David-A]

FlexRIOs are a little different than the R series modules. You do need to acquire data within a single cycle timed loop. Once you've acquired it you have the option of moving it into a while loop, though i wouldn't recommend it. There are a lot of reasons why that is, but in twenty words or less its because a 5781 is moving so much data that it's difficult to meet performance requirements outside of a single cycle timed loop. 

Take a look at the The NI LabVIEW High-Performance FPGA Developer's Guide for a good overview of programming an fpga inside a single cycle timed loop. The section "HIGH-PERFORMANCE PROGRAMMING WITH THE SINGLE-CYCLE TIMED LOOP" directly answers the questions you have about different types of loops in LabVIEW FPGA.

http://www.ni.com/tutorial/14600/en/

[newFPGAuser]

Cason and David-A:

Thank you for the very helpful responses. I am in particular reading the PDF you liked to, regarding optimization and how various design requirements are interrelated. On that note, is there any detriment to making copious use of local variables on both the HOST and FPGA VIs? Having a nest of wires is driving me nuts!

[David-A · Accepted solution]

If you've got a nest of wires you should look into clustering some of them together and then unbundling them when you need a specific piece of data. There are one or two good reasons to use local variables, and 100 bad reasons to use them. Avoiding a nest of wires falls into the bad category. Rather than using a local, look into how you can better group wires into clusters, and nodes into subVIs. How to do this is a little off topic from the OP, so I would recommend refining your question into "how can I better organize my top level vi so that I don't feel the need to use local variables" and then creating a new thread with a piece of example code. 

[Terry_ALE · Accepted solution]

You could group your data into clusters; this will reduce the amount of wires.

Local variables are generally discouraged because they break dataflow but on the FPGA can be handy for sharing slow changing data between multiple loops.  It is important to check the type of data you are using before using local variables as you may need to use something like a FIFO (which can be lossless as opposed to local variables which are lossy).

A good discussion on the topic of local variables: https://forums.ni.com/t5/LabVIEW/How-do-you-use-local-variables/td-p/3305477