Developing Proficiency with LabVIEW FPGA

[Christian_L]

Developing Proficiency with LabVIEW FPGA

Back to the LabVIEW FPGA Developer Developer Center

Learn the necessary skills to develop common applications and system components with LabVIEW FPGA.

FPGA to Host Communication

Topic	Format	Description
How DMA Transfers Work	Manual	How to stream data between FPGA and host application using DMA FIFO
Data Communication Methods in LabVIEW (scroll down for FPGA methods)	Manual	Reference table of LabVIEW communicationmethods
High CPU Usage When Reading Data from Target-to-Host DMA FIFOs	KnowledgeBase

Optimization

Topic	Format	Description
Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining	Tutorial	Video tutorials illustrating how to develop simple examples in LabVIEW FPGA
How Can I Optimize / Reduce FPGA Resource Usage and / or Increase Speed?	Webcast	Video slide show tutorial providing an overview of the LabVIEW FPGA module and how to use it
Optimizing FPGA VIs for Speed and Size (FPGA Module)	Tutorial	Description of how FPGAs work
NI LabVIEW High-Performance FPGA Developer's Guide	Tutorial	Recommended Practices for Optimizing LabVIEW RIO Applications
How Do I Change the FPGA Compiler to Optimize for Area or Speed?	KnowledgeBase
Optimizing FPGA VIs Using Pipelining (FPGA Module)	Manual
Optimizing FPGA VIs for Speed and Size (FPGA Module)	Manual

IP Integration

Topic	Format	Description
Importing External IP Into LabVIEW FPGA	Tutorial	Use a wide range of algorithms that are fine-tuned to Xilinx field-programmable gate arrays (FPGAs) to achieve high performance while taking advantage of code reuse.
Using VHDL Code With LabVIEW FPGA	Tutorial	Tutorial on using the CLIP node in LabVIEW FPGA to import VHDL into your VI
Importing HDL Code into FPGA VIs Using the HDL Interface Node	Tutorial	If you have a block of HDL code you want to use in an FPGA VI, you can enter the code in the HDL Interface Node rather than rewriting the code in LabVIEW.
Difference Between CLIP Node and HDL Node	KnowledgeBase	The HDL node and CLIP node differ in how they are implemented on the hardware, allowing the users more flexibility in how they would like to use any HDL code on their FPGA.
IPNet	Code	Collection of IP cores (sample code) for LabVIEW FPGA

Testing, Debugging and Simulation

Topic	Format	Description
Testing and Debugging LabVIEW FPGA Code	White Paper	Overview of simulation options in LabVIEW FPGA
Using the LabVIEW FPGA Desktop Execution Node	Tutorial	Creating test benches with accurate timing characteristics, concepts necessary to use the FPGA Desktop Execution Node.
Cycle-Accurate Simulation in LabVIEW FPGA	Tutorial	Simulate application logic for both functionality and timing; cycle-accurate simulators test the timing constraints of your logic
LabVIEW FPGA: Getting the Most Out of Simulation	Presentation	Take advantage of simulation tools to reduce the need for frequent time-intensive compilations
FPGA Debug Reference Library	Code	Collection of reuse VIs that can be included to make the debugging process both faster and easier