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##### Xilinx FIR Compiler Data input/output format

12-20-2017 01:54 PM

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How do I have 1.31 in and 1.31 out?

12-21-2017 11:54 AM

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Hi rykowski,

I looked at the FIR compiler documentation and noticed the following on page 59:

For this example the coefficients are signed with a coefficient width of 10 bits and a coefficient fractional width of 5 bits (using the Mathworks Fix format notation Fix10_5). The specified coefficients range between -12.34 and +13.88. Considering the coefficient bit width as integer only, 10 bits give a maximum positive value of 511 and a maximum negative value of -512. The fractional bit width is 5 bits; this gives a maximum representable positive number of 511/(2^5)=15.96875 and a maximum representation negative number of -512/(2^5)=-16. All coefficients are scaled by the factor 15.96875/13.88=1.1504863 (=+1.2176dB) prior to quantization. The overall scaling factor is calculated as defined previously and displayed in the Vivado IDE.

It looks like fix32_30 as you have in your screenshot represents 1 bit for the sign, 1 bit for the coefficient width and 30 bits for the fractional width. Have you tried making the input and output signed? I would contact xilinx and see what they have to say about how to define the FIR compiler.