Main Simulation entity HLD IP from VIVADO HLS

[Phy_comm]

Is there any documentation on .eip form for importing IP using HDL and IP-XACT .xml file?

I followed method given on http://www.ni.com/documentation/en/labview-comms/2.0/editor/external-ip-document/

I am not clear about:

1. Which file to choose for Main Simulation Entity?

When I import using xml file from configuration.xml of IP Catalog export of VIVADO HLS it automatically populates the field with file name same as top module.

Please help me choosing the file backed by proper reason.

2. Parse and verify method does not work when there are multiple files in ip. Sometimes it takes even .dat file!

It work well with single file (.vhd) in ip.

3. How to differentiate which file to choose in synthesis file and simulation segement?

I am primarily using design examples given under  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug871-vivado-high-level-synthes...  to generate RTL IP.

Sqrt example takes cordic_base_vhd as additional resource and simulation file. and works fine.

While other examples say atan2 does not work with incorrect import.

I am attaching exported ip here for atan2(not working) and sqrt(working).

[DECONN]

Hi Phy_comm,

I'll take a closer look at the examples you have. Also, were you able to get the HDL import examples projects included in LabVIEW Communications working?

[Phy_comm]

Yes the examples are working. Even my codes are working but when there is single vhd file.

[Phy_comm]

An interesting thing is happening here.

The example given in Comm suite: Vivado IP integration: Demo clip adder works both ways: using .xml file as well using the direct external VHDL integration using adding files one by one.

In my exported IP from VIVADO HLS for SQRT .xml import works but external IP addition does not work.

It give error as attached in the file.

Is there a particular pattern of VHDL coding which suits it?

My IP cannot recognise the HDL ports too when adding files one by one. Basically top.vhd should call all the dependent components I believe.

Whats the working method of this .EIP form?

[DECONN]

Hi Phy_comm,

Thanks for updating with those details. I'm still looking into it. While looking through your source files, I noticed that they appear to be generated in Vivado 2016.4. Is this correct? If so, would you be able to try generating the same files in version 2014.4? This is the version that LabVIEW Communications 2.0 uses. I'm not sure if that would be the direct issue, but it would help rule out any compatibility concerns.

[Phy_comm]

I actually used Vivado HLS because it has necessary C++ libraries. Can it be issue?

Can you cite me example/procedure of how Labview Communication 2.0 uses VIVADO to generate IP?

I will generate IP accordingly so that there is no mismatch.

[Phy_comm]

Hi!

As update I did use Vivado as you said. Previous works used IP from VIVADO HLS.

Now I used IP catalog of Vivado Hls in Vivado and then generated IP.

The good news is ports are identified now.

But when I use the IP in Comm Suite to give input and fetch output it fails to get xilinx:hls: (top module of the project)

Actually using this method(attached pdf for steps followed) design_1_wraper.vhd is taken as top module rather the actual file generated by the vivado hls like for dds example it should find xilinx:hls:dds_top.

Whats cause of this error?

The error snapshot is attached.

 The pdf followed as steps is also attached.

[Phy_comm]

What I conclude till debugging now is that generating IP from VIVADO helps identify the HDL port correctly and there is no error in .eip file as previously.  But when running FPGA it compile FPGA and returns error:

Error occurred while generating IP support files.

ERROR: [Coretcl 2-1134] No IP matching VLNV 'xilinx:com:hls:sqrt_top:1.0' was found.

The IP file is attached.

[ks30]

Hi Phy_comm,

Thank you for the update. I will take a look at your latest source files.

We are still looking into this issue and will update you via the support channels when we have a suggestion with how to proceed.

Regards,

Kyle S.

[Phy_comm]

Hi! Kyle!

Thanks for updates. I am eagerly waiting for leads. Meanwhile can you help me check if you can use the example of VIVADO IP to import and use IP generated from HLS or Vivado in FPGA diagram?

I guess that example itself contains an imported IP. It should be known how it was generated.
This would clear if any step is being missed.attached pdf has recommend steps