UART communication between FPGA(DE0) and PC

[sea_of_electron]

Hi everyone and sorry for my poor English.

*Progress
I am developing measurement system on FPGA board(DE0) to communicate with 24bit-ADC(AD7190) via SPI and send digitized data to PC via UART(CP2012 : SiLabs is used). Also I am developing application which receive data from FPGA by UART and display it on graph by using Labview. And measuring condition is below.
*number of bits = 24(bit)
*sampling rate = 10(sps)
*baudrate = 19200(bps)
About UART settings in Labivew, the default settings are used exclude baudrate.

*Problem
When I use some terminal software(ex. Teraterm) for debug, I was able to receive 24bit-data(actually 3 byte) successfully without packet loss. But when I did same thing by Labview, sometimes packet loss was occurred randomly as shown in Fig. 1 and Fig. 2. In the both figure, return counts means how many bytes were received.

*Questions
How should I do to improve packet loss??
I want any comments or advices...

*References
I attached the screen shot of application's block diagram.

Thank you for reading
Yuki

[Albert.Geven]

Hi

If you always send 3 bytes and are sure that those 3 bytes are not a mix of 2 bytes before and 1 after the split or 1 byte before and 2 after the separation you also can read all that is avalable (at least 3) and buffer that.

If you send the real vi instead of a png I can change some beginner mistakes that are easy to speed up.

But calculation speed is probably not the problem, operating system respons may be a problem.

[sea_of_electron]

Hi, Albert.

Just in case, I decoded UART's packet on my oscilloscope and result is attached as figure called "debug_result". 

I selected one of the ADC's internal register which has 0x553EF0 as default value, and I got this at "LSB first".

As shown in figure, data packets are divided 3 bytes and expected value are gotten.

In addition, these packets were acquired steady when I decoded continuously.

So I think packets might be sent by correct format.

And I attached my VI for you.

NOTE : My FPGA does not issue termination character although it is declared in VI.

Last I have additional question.

Should I consider about using RTOS for this system if there is problem at OS respons?

Thank you

Yuki

[Albert.Geven · Accepted solution]

Hi

Thanks for sending the vi.

The real problemis in the write to textfile. The opening of the file and write a float value as an array is probably blocking the reading of the bytes coming from the fpga resulting in lost data. It helps that the serial line is buffered by the system. But also your stopping criterium is a bit blunt but effective.

Check the producer consumer example on how to solve this.

In fact by having a while loop for reading the data and another whle loop running in parallel to write the data.

The communication between the two loops can be done by a queue, wires coming from one loop going to the other loop would break the parallelism, so look carefully to follow the example.

Some minor points:

instead of converting a byte to an array of bits and converting this to a reverted string you can show the bits directly by displaying as binary in a field of 8 with the zero values shown on the left. see the snippet in writing bits to frontpanel.

Also if the first index of an array is not connected it defaults to zero, and each next index is automatically incremented.

These changes are not generating a big effect on your timing but makes reading your program easier.

[sea_of_electron]

Hi

Thanks for your reply.

According to some NI's technical note, Many process in ONE ROOP easily leads to low paformance as you say...

So I will consider about using queue or parallel process techniques. 

And thank you for minor points advice!

it truly makes source code easilier.

Thank you.

Yuki

[juliolop]

HI, this is Julio, I saw these old posts and decided to contact you, I need help, I'm desperate trying to communicate a DE0 FPGA with a computer, I'm new using FPGA and all I have it's the file (diagram in Quartus II) I need to get it running, it's a piece of test equipment I inherited and really need to see it running.

supposedly the FPGA after be programmed ( I know how to do it) is able to set a group of relays in different configurations depending the byte it receives through the RS-232

I would like to receive this byte back in the computer and show it in the 7 seg displays in the form (CF.##)   

can you help me?

I'm attaching the project for your evaluation.

bets regards

[BigApple0]

Hi Julio,

Your project looks a little more complicated than the OP's.  Looks like you need help with the FPGA code in addition to the LabVIEW serial driver running on the PC.  I may be able to help.  Shoot me a PM.  I've worked with Quartus II, Terasic FPGA boards, and LabVIEW serial drivers.  I'm not sure I can do everything for free (looks aerospace related?) but may be able to help get you started in the right direction and give you some helpful advice.

[juliolop]

Any help will be highly appreciated, this is a project I would like to get running on, Labview is not used.

I have the FPGA connected with a five wires connection to the RS-232 in the computer and none code I've used look operative

one question.

how do I set up the UART speed in the FPGA?

regards

[BigApple0]

The baud rate is based off of the 50 MHz clock onboard the DE0.  The 50 MHz clock runs through several clock dividers to generate TX and RX clocks.  The TX and RX clocks drive parallel-to-serial and serial-to-parallel shift registers in the serial port.

Do you have the original files?  It appears some files may have been added/edited recently which broke the design.