Hi you all
I measure the angular position (crank angle of a CI engine) by acquiring the signal of an angular encoder (photointerrupter on a slotted disk with 900 slots/rev. = 0.4° resolution). In order to interpolate the angular postion (to get a better resolution for controlling the intake/exhaust valves of the CI engine precisely) the idea is to use some sort of PLL to track the encoder signal (TTL) and generate a (locked) signal with a frequency which is four times the frequency of the encoder signal (= 3600 pulses/rev. = 0.1° resolution). Since a cRIO-9082 is used for control purposes anyway I prefer to implement the PLL on its FPGA directly (with a NI 9401 for the TTL input of the encoder signals) without using any third-party hardware. Fortunately I found a PLL implementation (Costas loop) from the LabVIEW FPGA RF Communication Library 2.1 and tested it successfully with simulated (noiseless) square wave signals. Due to fabrication tolerances of the slotted disk the frequency of the real encoder signal is not perfectly constant (at a constant rotational speed) which might be a problem for the PLL (maybe a general problem or just a matter of tuning the PLL parameters (e.g. filter parameter) etc.
Since my knowledge in this field is very limited (DSP in general) I would like to ask some questions here:
(The rotational speed will be in a range from 200 to 1800 rev./min hence the frequency of the encoder signal (CDM) is around 3 to 27 kHz but only operating points with constant speed need to be considered.)
Any help and advice is highly appreciated.
Thanks a lot!
I dont know the implementation you are refering to, but I guess they assume a signal of constant frequency, so I cant tell you if there are any drawbacks in using this implementation.
As far as I understand you want to quadruple your input frequency (digital signal). So the easiest implemtation I could think of is that you have two loops:
In my scenario the phase of the output wont be synchronous with your signal.