Measuring Fast Opamp Rise Time with NI 5162 Digitizer in STS System – Cable Capacitance Impact

[pavijoshi421997]

I'm working on characterizing a high-speed opamp in an NI STS test system using the NI PXIe-5162 high-speed digitizer. The expected rise time is around 3 ns, and the slew rate should be approximately 2000 V/μs. However, in practice, I'm observing a slower response — rise time is longer and the measured slew rate is only around 1400–1500 V/μs.

I suspect the issue is due to the high capacitive loading introduced by the coaxial cable connecting the DUT on the PCB to the digitizer input. This added capacitance seems to be degrading the signal integrity and slowing down the edge transitions.

Has anyone faced a similar issue in STS setups? What are the best practices or recommended techniques to minimize the impact of cable capacitance when measuring fast signals like this? We cannot go with shorter cables since it is a NI STS test system. 

Any insights or suggestions would be greatly appreciated!

[santo_13]

Any electrical parameter that is degraded by higher cable capacitance and cable length is not the right parameter to measure in Production Test on an ATE.

In some cases, you need to re-implement an Analog Front End of the instrumentation close to the DUT to eliminate the effects of long cables. Use of active probes is an alternative but not practical in production test on ATE with Loadboard.

Can you characterize the limitations of the STS signal path with a known good DUT and revise your limits accordingly stating instrumentation limitation?