FieldPoint Family
FPGA Target issues
Hi,
I am facing the multiple problems on my system after recompiling the FPGA vi. I
I have the following:
PXI RT Controller 8196, PXI 7833 R connected to a few cRIO modules. Things were working perfectly until we had to modify the FPGA VI. Upon Compilation, it started giving me this error. I have already tried the following:
when I go into the project explorer and right click on the FPGA device and click reset
Please someone assist on this.
Regards,
Ashm01
I am facing the multiple problems on my system after recompiling the FPGA vi. I
I have the following:
PXI RT Controller 8196, PXI 7833 R connected to a few cRIO modules. Things were working perfectly until we had to modify the FPGA VI. Upon Compilation, it started giving me this error. I have already tried the following:
- Repaired RIO (No luck)
- Repaired VISA (No luck)
- Repaired FPGA (no luck)
- Repaired LV RT (no luck)
- ReFORMATTED PXI Controller and reinstalled all software (No luck)
- Ensured that VISA is able to access the PXI 7833R by going into MAX and checking whether I can read/SET vaues. (That works)
- In the process it cannot now load the NI-DMM DLL's. (Disabled DMM code) but still no luck.
| −1073807346 | The given session or object reference is invalid. |
Please someone assist on this.
Regards,
Ashm01
Hi Adnan,
I had the FPGA VI along with the whole project compiled in another PC for testing and then finally moved it on the intended target.(Same configuration). Like I had mentioned, everything was working fine until I had to recompile the VI due to changes. Since then, I started receiving the mentioned error. I had already check the properties and the RIO0::INSTR was already there.
In another thread, someone else was receiving the other related error code and he mentioned to disable automatic close VISA settings. I did the same in the Project RT Target and within the labview options. Rebooted the PC and PXI chassis and the RIO device was accessible.
I clicked on reset and no error dialog boxes either.
To be curious, I reenabled the automatic close VISA settings and it still works normal.
I never realized how significant this checkbox turned out to be in this version .
Thanks,
Ashm01
I had the FPGA VI along with the whole project compiled in another PC for testing and then finally moved it on the intended target.(Same configuration). Like I had mentioned, everything was working fine until I had to recompile the VI due to changes. Since then, I started receiving the mentioned error. I had already check the properties and the RIO0::INSTR was already there.
In another thread, someone else was receiving the other related error code and he mentioned to disable automatic close VISA settings. I did the same in the Project RT Target and within the labview options. Rebooted the PC and PXI chassis and the RIO device was accessible.
I clicked on reset and no error dialog boxes either.To be curious, I reenabled the automatic close VISA settings and it still works normal.
I never realized how significant this checkbox turned out to be in this version .
Thanks,
Ashm01
