Power Servoing Example for the NI PXIe-5644R

[Ryan_V[DE]]

Power Servoing Example for the NI PXIe-5644R » This example uses an FPGA-based control loop to rapidly adjust VST output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.

Description: This example is designed to level the output of an RF power amplifier by iteratively measuring its output power and adjusting the supplied stimulus. These measurements and adjustments are performed continuously, as opposed to traditional techniques which make these measurements and adjustments in series, with significant latency between each. The parallel leveling in this IP is able to achieve much faster performance than traditional methods, placing the power amplifier into a known state so that subsequent measurements can be performed, decreasing overall test time.

Additional Documentation:

• After installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\examples\NI Power Servoing Example for the NI PXIe-5644R\documentation\Hardware Power Leveling for PA Test.pdf

Compatibility:

• LabVIEW Version: 2012
• Hardware: NI PXIe-5644R

Dependencies:

• NI LabVIEW 2012 Support for NI PXIe-5644R 1.0 (NI MSI installer)
• Power Servoing IP (automatically resolved through VI package)

FPGA Footprint:

Xilinx Virtex-6 LX195T

• 38.6% / 48230 LUTs
• 23.2% / 57845 Flip-Flops
• 39.5% / 136 Block RAMs
• 33.0% / 211 DSP Slices
• >90% compile success rate

Latest Version:

• Power Servoing Example for the NI PXIe-5644R 1.0.0 (LabVIEW 2012)

Previous Versions:

• none available

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