DSP
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Channel Emulation IP »
This IP implements inline, real-time DSP in LabVIEW FPGA to apply arbitrary channel models to RF data. Fading profiles are computed in real-time on the host, and dowloaded to the FPGA where they are interpolated and applied to the data stream.
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Control
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Power Servoing IP »
This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input.
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Digital Protocols
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I2C IP »
This IP implements inter-integrated circuit (I2C) communication, including support for both master and slave functionality.
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SPI IP »
This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality.
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RFFE IP »
This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality.
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Ryan Verret
Product Marketing Engineer
Signal Generators
National Instruments