This IP uses an FPGA-based control loop to rapidly adjust device output power to reach a desired input power, when an load or amplifier of unknown gain is connected between the output and input. |
This IP implements inter-integrated circuit (I2C) communication, including support for both master and slave functionality. |
This IP implements serial peripheral interface (SPI) communication, including support for both master and slave functionality. |
This IP implements MIPI RF front end (RFFE) communication, including support for both master and slave functionality. |