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This document explains how to install, configure, and test the National Instruments universal software radio peripheral (USRP) 294xR or 295xR device with the new Ethernet-based Reference Architecture. This Reference Architecture configures the USRP RIO and passes TX/RX data all through the Ethernet Port while having a customized FPGA code pre-deployed.
This updated version splits the project into a Host Project and an FPGA Project. This has been done to allow for the modification and compilation of the FPGA but the compatible environment for the FPGA project is limited to LabVIEW 2015 SP1 due to the limited compatibility of the FPGA CLIP and the Xilinx IPs with the Vivado compilation tools.
The Host project does support the latest LabVIEW versions starting with LabVIEW 2021 SP1.
(*) TwinRX USRPs are not yet supported by this architecture.
To use the NI-USRP instrument driver, your system must meet certain requirements. Refer to the product readme, which is available on the driver software media or online at ni.com/manuals, for more information about minimum system requirements, recommended system, and supported application development environments (ADEs).
You must be an administrator to install NI software on your computer.
(*) You can find the recommended 10Gbit Ethernet card in this link for the PCIe version. For the PXIe version, you can find the recommended card at this link.
(**) This PCIe-MXI interface kit will only be used to deploy the bitfile to the Flash of the USRP RIO the first time
(***) Considering that we are changing folders and deploying the project, you need to specify the new locations for the project dependencies
You need to install the required software for the FPGA project on a separate computer or virtual machine. This setup will only be used to modify and compile the FPGA. You must be an administrator to install NI Software on your computer.
You can either use the already compiled bitfile that matches the last version of the main FPGA VI or recompile the FPGA if you want to bring additional functionality to the FPGA personality.
(*) Compiling the FPGA locally is subject to limitations if your operating system is Windows 10. Make sure to check this link for the compatibility of the compilation tools with Windows 10.
Install all the software that you plan to use before you install the hardware.
You must configure your 10Gbit Ethernet Card to accept large packets:
(*) The USRP RIO that you will be using should already have on its flash the bitfile shipped with the Reference Architecture
The default IP address for the SFP 0 Port of the NI 294x or NI 295x is 192.168.30.2.
Host Ethernet interface static IP address
Host Ethernet interface subnet mask
Default SFP 0 port device IP address of the USRP
You can change the IP address of the SFP 0 port of the USRP by the following steps:
NOTE: Make sure that the default personality is the one deployed on the FPGA
(*) The default IP Address of the SFP 1 port of the NI USRP RIO is 192.168.40.2
This reference architecture comes with an open source LabVIEW FPGA code which allows you to add your customization to the FPGA code while keeping the 10Gbit Ethernet support. You can either directly flash the provided bitfile ‘Ethernet Full Support Xcvr.lvbitx’ in the FPGA bitfiles application folder which supports 10Gbit Ethernet or build from the source FPGA. After compiling your FPGA code, you can deploy its bitfile to the Flash of your device by the following steps:
The new bitfile is loaded now on the FPGA of your device.
You can run the Reference Architecture by following the below steps:
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
Very interesting project; i don't know if i have done something wrong or not, but i followed all the procedures and i can't execute the template due to an error on " niUsrpRio Config v1.lvlib: Chekc Data Clock Rate and Bandwidth - Ethernet.vi": Type Definition 'Daughterboard ID': Type definition not found or contains errors - The master copy for this type definition could not be found or the master copy has errors. You must find and fix the master copy, or right-click this type definition and select Disconnect. Could you tell me how to solve this error?
Moreover, if i change the FPGA script, could i load it on board with UHD using ethernet connection?
Thanks for the help!
I've followed the procedure and i've loaded the bitstream into the device, but when i ping the device, i receive no answers; it seems that the device is not connected, also because the device is not listed on configuration utility tool. Can i have some advices in order to use this code?
My scenario is a NI USRP 2954R connected with MXI cable to a PC with NI PCIe 8371, and the ethernet connection based on ethernet cable connected to the USRP with a SFP+ to Eth adapter on port 0, and a usb network adapter on PC side.
I'm also unable to execute the host VIs as I've also encountered the same error as mentioned above. Following are the errors that I get:
1) "NI USRP driver support for LabVIEW 2019 is missing and is referenced by the following VIs:
-C:\Program Files\National Instruments\LabVIEW 2019\instr.lib\niUsrpRio\Config\v1\Host\Private\Check Data Clock Rate and Bandwidth - Ethernet.vi
When I open the above VI, I get the following list of errors:
2) This VI is connected with a library that does not include the VI. The VI might have been deleted from the library. Add the VI to the library again or select File»Disconnect from Library.
3)The master copy for this type definition could not be found or the master copy has errors. You must find and fix the master copy, or right-click this type definition and select Disconnect.
4) When I opened the host VI, I also noticed that the VI was unable to find a .ctl file and loaded the VI without it. I manually browsed to that directory and couldn't find the .ctl file it was looking for. This is shown in the snapshot below.
Kindly advice me how to get around this issue. Any advice or help will be really appreciated.
Thanks in advance.
I have resolved the aforementioned issues by adding all the ethernet-based VIs in the library (niUsrpRio Config v1 Host.llb). You can select skip in the dialogue that appears for password protected VIs when adding them to the library.
Ethernet VIs can be found in the Public and Private folder found in this path:
C:\Program Files\National Instruments\LabVIEW 2019\instr.lib\niUsrpRio\Config\v1\Host
Also, usrpDboardld.ctl file is located at the path given below. Make sure to manually browse and load this file when you open any host template VI.
C:\Program Files\National Instruments\LabVIEW 2019\instr.lib\niUsrpRio\Config\v1\Host\Private\usrpDboardld.ctl
I am using USRP X310 with Twin RX Daughterboard.
What kind of changes i should made in the given example code "USRP RIO Full Ethernet Support.zip 18429 KB" to run this code on my target.
This example code just do not compile without any changes. It returns error during intermediate files creation, saying labview cannot determine data size in several places. I double and triple-checked it, tried LabVIEW versions from 2019 to 2021. It seems that the dependency on niInstr Ethernet MAC - CLIP v1.lvclass or niInstr AXI4-Stream Reader/Writer v1 FPGA.lvclass changed since this architecture was created. I tried modifying the involved VIs assuming the sizes of tdata or tkeep to be largest possible (high-throughput streaming), and was able to compile the bitfile, but the communication with the target does not work with my changes.
BTW the bitfile provided with this architecture works well providing IQ data over ethernet. Which means, the FPGA VI is OK to compile on some circumstances (e.g. compatible dependency versions).
Is there anyone succeeded with compiliung the working bitfile?
A new version of the architecture has been uploaded and should allow you to work around the issues encountered with the compilation of the FPGA VI. The core IP used in this project is only compatible with LabVIEW 2015 and the corresponding Vivado compiler, it is the reason why in this new version of the architecture, the host and FPGA project has been split. The FPGA project will remain on LabVIEW 2015 to allow recompilation while the host project can be used in the latest LabVIEW versions starting LabVIEW 21.