To download NI software, including the products shown below, visit ni.com/downloads.
Overview
LabVIEW FPGA VI and example showing how to generate pseudo random numbers using a linear feedback shift register algorithm.
Description
The Pseudo Random Number Generator VI is built as an IP core for LV FPGA and can be used in a variety of applications. The VI is set to be reentrant so that it can be used multiple times in an application.The linear feedback shift register algorithm used to generate the pseudo random number is explained in detail in this Wikipedia article.
Requirements
Steps to Implement or Execute Code
To simulate this algorithm on a development computer:
To implement this on an FPGA target:
Additional Information or References
VI Snippet of Pseudo Random Generator 2012 NIVerified.vi
VI Snippet of Pseudo Random Number Generator (FPGA) 2012
**This document has been updated to meet the current required format for the NI Code Exchange. For more details visit this discussion thread**
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
Thanks for idea!
Unfortunately, this generator does not work in LabView 2019 in cRIO/FPGA simulation mode. It returns always 0. Probably this is due time/tick counter giving first value equal to 0.
A little modification to make it run on cRIO-9048 "simulated RT/FPGA mode" in LabView 2019. (for unknown reason I cannot add VI as an attachment).