PCI 6602 register document needs clararification

[Jasmine1688]

Hi,

I have a few questions regarding PCI 6602 register level programming document:

1. I am doing simple gated event counting (level gating, counting once). I basically arm, gate on, gate off, disarm, read the counter, and then arm again and the cycle goes on. Do I need to load the counter with LoadA or LoadB content between arm and gate on? From another document I found online, it seems that reloading happens automatically. But I tried in my code and it seemed that I needed to reload every time.

2. On page 87 and 88 of NI 660X Register-Level Programmer Manual. First of all, this covers PFI 0 to 39. So the table on Page 87 should end at 0x7A2, not 0x7A0, right? On page 88, A means PFI 0, 2, 4, 6, …, 38 and B means 1, 3, 5,…, 39? For PFI 0 to 7, if I configure them as output, I should be able to write to STC DIO output register to program them to be high or low, right?

3.  On page 38 of NI 660X Register-Level Programmer Manual, Chip Signature Register is 0x700. On page 39, its address is 0x73C. Which one is correct? What should the chip signature be?

4. If I set a counter's gate input as its gate pin, do I need to set the same pin as a PFI input line?

5. After soft_reset, what are the default values of all registers? all 0s?

[Jasmine1688]

Hi,

I have a few questions regarding PCI 6602 register level programming document:

1. I am doing simple gated event counting (level gating, counting once). I basically arm, gate on, gate off, disarm, read the counter, and then arm again and the cycle goes on. Do I need to load the counter with LoadA or LoadB content between arm and gate on? From another document I found online, it seems that reloading happens automatically. But I tried in my code and it seemed that I needed to reload every time.

2. On page 87 and 88 of NI 660X Register-Level Programmer Manual. First of all, this covers PFI 0 to 39. So the table on Page 87 should end at 0x7A2, not 0x7A0, right? On page 88, A means PFI 0, 2, 4, 6, …, 38 and B means 1, 3, 5,…, 39? For PFI 0 to 7, if I configure them as output, I should be able to write to STC DIO output register to program them to be high or low, right?

3.  On page 38 of NI 660X Register-Level Programmer Manual, Chip Signature Register is 0x700. On page 39, its address is 0x73C. Which one is correct? What should the chip signature be?

4. If I set a counter's gate input as its gate pin, do I need to set the same pin as a PFI input line?

5. After soft_reset, what are the default values of all registers? all 0s?

[Steven_T · Accepted solution]

Hello,

The register level programming document download should be next to the download for the driver development kit that includes examples using the registers described in the document.  Some of my answers will point to these source files.

https://decibel.ni.com/content/docs/DOC-16444

1. The Gi Mode Register includes bits that allow you to automatically reload the counter register based on the Gate(Gi_Loading_on_Gate, Gi_Reload_Source_Switching). If these are not the behavior you want, you should have your software manually load the value.

2a. You are correct about there being another register at offset 0x7A2 for PFI 38 and 39. Check tTIO.h line 5610. The enum in this class contains the offset for the register this class represents.

2b. Yes, this is possible. The Simple Digital I/O portion of the NI 660X Register-Level Programmer Manual has information about how to accomplish this.

3. The offset of the Chip Signature Register is 0x700. See tTio.h line 7340 for the offset enum to confirm.

4. Example gpct_ex2.cpp shows how to use the default gate and pin for clock 0. It does not need to set the PFI as an input.

5. It does not say in the documentation what happens in this scenario. I would recommend starting over with all of your access to the board, in order to make no assumptions about the state of the registers.

I hope this helps,

Steven T.