I am working on trying to do some data acquisition with an NI-6545 installed in a 1095 chassis. I am supplying the chassis with a 10MHz reference source that is generated externally and also distributed to an A to D converter which uses the same clock as an encode clock. The A to D is constantly outputting digital data when powered on and being supplied the 10Mhz clock. I can supply the A to D with various high precision signals both DC and AC. When I do a continuous read, or any read, from the A to D over the 6545 then reassemble the bits, the data I am getting back has significant distortion or noise. If I mess around with my sample rate enough the distortion eventually goes away and will work fairly well until things are powered down and turned back on or some other setting is changed which causes the code to recompile. This is leading me to believe that it has something to do with the sample rate and reference clock synchronization or something. I need some ideas on how I can resolve the issues. I have attached how I am doing the acquisition now, and a few images of what the "noise" looks like.
I tried using HSDIO SClk Relative Delay, but with the sample rate set at 200MHz (which is what I want) that gives me +/-5ns and advancing/retarding the delay in 1ns increments didn't seem to have any effect at all.
One of the digital signals returned from the A to D is the clock signal it is using for the encoding, so I don't know if I could somehow use that for synchronizing my ref clock/sample rate to help eliminate delay or skew? Or if I can somehow trigger to read the data from the other DIO lines based on the clock signal DIO line?
