Generating sample clock of lower frequency HSDIO

[jimmy1991]

I have a PXI-6541 card which is used for digital outputs. I can use the onboard clock of this card to time the output at a clock frequency of 25MHz. I have other cards, a PXIe-6341, PXI-6723 and PXI-4462 used for analog inputs and outputs that need a clock frequency of around 100 kHz. I would like to somehow use the clock from the 6541 card to properly synchronise the cards. Is there a way I could generate a clock signal of a lower frequency on a PFI channel from the 6541 card or do I need to use an output channel.

Alternatively, if I used the 10 MHz clock from the PXIe chassis and had each card sample this at their own frequency would this be enough to ensure the cards are properly synchronised?

Many thanks

[Alexander_Sobolev]

Check MAX -> board -> device routes tab if 6541 has DevX/DO/Sample clock terminal and where it can be connected (usually RTSI line). Then you can connect to this line on your other devices. Then you can use counter to divide frequency to get 100 kHz from 25 MHz and use its output as a common clock (through another RTSI) for other tasks.

Also to be sure all tasks start from one edge, you can pause this counter task or generate ARM trigger.

[Alexander_Sobolev]

One more thing. 

You can set timebase source and divisor (Timing property node -> Sample Clock -> timebase) for the task, but to synchronize phase, you need common signal anyway.

Check Multi-Device Sync-AI and AO-Shared Timebase & Trig-DSA.vi in examples 

[jimmy1991]

After looking at the device routes tab for the 6541 card, I cannot see the DO/SampleClock channel, so I am not sure if the SampleClock can be exported to the PXI backplane. I've looked at the options for configuring the sample clock for this card and the only PXI source is the PXI_Star line. However, I don't think the DAQ cards I have can be configured to use the PXI_Star line.