pulse configuration with PCI-6052E MIO card

[bernie schattka]

Help !

I would like to program one of the GPCTR counters on our PCI 6052E MIO daq device. There exists a high-level VI called 'Generate Delayed Pulse.vi' which is basically what I need, but instead of having a pulse delay, the output needs to be high (phase 1) at a leading edge of a gate signal and low (phase 2) following phase 1. The polarity of the ouput can be set so that it is reverse of the default, but  the ouput of the counter must be a digital low  when  waiting for a gate signal, or upon the completion of a cycle.

Thanks in advance.


   -bernie

[G_Lo]

bernie,

It sounds like you would like to use the counter's gate as the trigger for digital pulse generation.  I would suggest looking at the example "Gen Dig Pulse-Retriggerable.vi" in the LabVIEW example finder.  The example finder can be located at Help>>Find Examples in LabVIEW.  The trigger source would need to be the gate of the counter but please keep in mind that counter 0 gate is PFI9 and counter 1 gate is PFI4.  Also, the trigger source needs to be a RTSI, PFI or PXI line to function correctly.  For example, if you are using counter 1 and would like to trigger a digital pulse when the counter 1 gate is high then select PFI4 as the trigger source on the front panel.