Hi tlee16 -
If you probe the wire coming out of your "Format to SPI" VI, you'll see this:
Since you provided an input parameter of "Slave address = 0" (when the control is disconnected, it takes its default value), we can look at this waveform and deduce the role of each line:
0 --> CS_1
1 --> CS_0
2 --> MISO
3 --> MOSI
4 --> SCLK
Since you're not using the HWC engine, you only need to split this signal up into input lines and output lines, then wire the output lines to the "Run Core Device" VI in the same order as they are mapped in the HSDIO hardware. Your HSDIO mapping order is [CS_0, CS_1, MOSI, SCLK]. So we need to extract lines (0, 1, 3, 4) and reorder them to [1, 0, 3, 4]. I think this is the array that should be input to the "Digital Signal Subset" VI, though I haven't tested it.
Regarding the initial and idle states of each output line, those define what the device does with its I/O drivers when it is in the initial state or the idle state. These states are defined in the Digital Waveform Generator/Analyzer Help file; you can read about them online here. "1101" means that your initial/idle states for each line will be:
CS_1 --> '1'
CS_0 --> '1'
MOSI --> '0'
SCLK --> '1'
David Staab, CLA
Staff Systems Engineer
National Instruments