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BreakPoint
Monthly Bugs, May 2016
Continued from the April 2016 bug thread
The posting rules are as always:
- Each post here should only contain a brief description of a bug, together with a link to the thread where it is being discussed.
- One post/bug!
- One bug/post!
- No discussion of bugs. All discussions of a bug must take place in the original linked thread.
CAR#589373
Filed through NI support, so no discussions to link to. In LabVIEW FPGA, if you use Max & Min with an array, you will get a Xilinx compile error (RTL Elaboration failed). You will not see the error until Xilinx starts sythesizing. Found with LabVIEW 2015 SP1 with a Vivado compile.
