Hi,
The sampling rate in the FPGA mode on myRIO is not 25ns. 25ns is the clock tick corresponding to the Base clock of 40MHz timing the FPGA. Now if you want to sample a simple digital input that can be done in LabVIEW FPGA using a Single Cycle Timed Loop and can be achieved within a single clock tick(25ns) because all you are doing is to sample a single bit(using a comparator) but to sample an analog input you need multiple clock ticks typically of the order of some 10s of microseconds but this is something that varies from hardware to hardware depending upon the resolution of the ADC and needs to be benchmarked for myRIO.
What you can try is to place a normal while loop in LabVIEW FPGA with an Analog Input node inside it and try to benchmark the loop timing using tick counts. This shall give you an idea about what is the maximum sampling rate you can achieve on LabVIEW FPGA without any code inside the loop. Of course the code(logic) inside the loop will also limit the loop rates.
