FPGA simulated I/O Recive error -61399

[vgravel]

Hello,

I'm trying to simulate a cRIO-9073 on my development computer. I want to use the simulated I/0 features. If I use the random data, I have no problem to run my simulated VI. If I use the "Use Custom VI for FPGA I/O" option, I always get the error -61399.

I already had a look at this Link but and use a template VI but it doesn't change anything. I also had a look at the tutorial explaining how to do it but with no luck...

Any idea?

Thanks!

[A_Patel · Accepted solution]

Hi vgravel,

Did you also that the " Custom VI has been configured for every I/O item that you are using in your FPGA code"?

FLash

[vgravel]

Oops... that was indeed the problem...

Sorry about that and thanks for the help!

Vincent

[213124qwrad]

Hi,
I have a same problem. I tried to do according to the instructions stated above.

http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpgaconcepts/test_bench_tutorial/

My FPGA project has only 2 I/O that would be AI0 and AO0.

What I need to do is add data earlier acquired  by DAQ card for testing  purpose.
What I did  create a new VI from  Template. I have modified:

In "Running" case of Execution Stage...

1)Duplicated the case in I/O case structure. Named it Input.

2) Did the same thing for Node or Element Type Case. Named it Read I/O.
3)Removed the Report suppor (connected tunels)

4/5/6  same steps as in 1 2 3 just naded Output and Write I/O.

7) In Read I added Random number and afterwards build array (just for testing purpose)

😎 In Write -- I did nothing. I just don't get it why do I need to make a local variable in this case. (I did create it but) haven't used it.

If U don't mind please give me a hint here. I would like to run a simulation as soon as possible and finish my degree ;/. What did U mean by  " Custom VI has been configured for every I/O item that you are using in your FPGA code"?. Thougth it was done by setting up cases ;/.

Print screens:

[213124qwrad]

Think I know what was done wrong.
Input Output names should has the same name as the I/O staded in project explorer.

I just renamed the case names to the names of the connectors. Think it works. Now I just need to add the data. Regards.