Connecting SSI Instrumentation to a Compact RIO

[RobF]

Hi Guys,

I have several SSI instruments such as rotary encoders and displacement transducers avavailable to use and I want to be able to connect one or more of these instruments to a Compact RIO. Can anyone point me in the right direction in terms of what "C" module I would require? Taking the rotary encoder as an example, it outputs 10-30 VDC.

I have had a look at the 9411 and 9423 modules but the pin outs only have connections for the positve digital input signal and a common per channel. The instrumentation I am trying to connect has 5 connections: Data +, Data -, Clk+, Clk -, and Ground. I have had a look through some previous posts and it looks like I will have to communicate directly with FPGA via a serial connection?

Thanks in advance for your help

Regards

Rob

[Jamie_S.]

Hi Rob,

Thank you for your post regarding reading in data from your "Synchronous Serial Interface" rotary encoders for analysis within your cRIO.

Having read the requirements for SSI it is my understanding that you would require a bidirectional C Series module like the NI-9401 (100ns I/O resolution).

You will need to convert the RS485 (10-30V) voltage levels to TTL (0-5V) to allow for communication and to prevent damage to the NI-9401 module. You will also need to perform processing on the FPGA of your cRIO to enable SSI data to be read/written. Some example code has been posted in the NI Community demonstrating generating and reading using the SSI protocol. In a typical system the SSI data is sent by a sensor and will be read by the FPGA device for use in the application.

The NI Community Example "LV FPGA SSI" is available here.

Hopefully this assists when choosing hardware for your SSI application Rob.

Many Thanks

[AndyClegg]

I'm looking at the difficulty or otherwise of connecting SSI transducers, and this suggestion of using a module which has incompatible signal levels sounds a bit messy, though nothing sounds too easy.

As there isn't any standard SSI hardware / software, if anyone has any experiences about using SSI with cRIO it would be really good to hear about them. From my initial look at this, it seems there are three options:

1) Use a NI 9871 (4-Port RS485/RS422 Serial Interface Module), which probably requires us to code (in FPGA) the SSI clock and data reads onto the module outputs directly. I can't see any mention of SSI being an option within the standard LV blocks to save on this programming myself.

2) Use two modules - a DO for CLK and a DI for DATA (none of the bidirectional modules have compatible signal levels) and with fast enough response (at least 10microsec to give a 100KHz clock), and program the code in FPGA to do the SSI clock and reads. I think that is what the LV FPGA SSI (Synchronous Serial Interface) Protocol is for - but could be wrong.

3) Use the third party cRIO 4422 Module - which is a four channel serial module which supports SSI. But again it looks like it needs to be coded in the FPGA to access the data - though it does say "FPGA code for SSI and RS232 protocols can be provided on request", so the problem there is not knowing how easy this will be to adapt and actually get the numbers out and at the update rate we want. It still may need a lot of programming by us.

I am really unclear about how much effort / cost this is going to take, and hence the trade-off between going this route or suggesting a standard 4-20mA analogue signal but suffer some degradation in accuracy of the data we get.

Thanks in advance.

Andy Clegg

[AndyClegg]

No immediate need to reply now, as this will use a normal 4-20mA analogue signal now.

However any comments about the SSI stuff would still be useful to know, as I am sure it will crop up again. Thanks,

Andy

[KelvinH]

Hello:

I need to conect two absolute SSI encoders to the NI 9401.  The encoders are the Kubler T8.F3653.1521.B712.  and the T8.F3663.1521.B722 I expect the CLK required is 2Mhz for both, one is a 17Bit, the other a 24Bit.?

1. Bandwidth limits?

2.Can the FPGA code be modified to support this?

3.HAs anyone tried it?

[FrankyCam]

I used the NI9401 and little bit modified SSIFpga program and i could red the signal from a 12bit SSI encoder by Eltra. I needed to convert the signal level from rs422 to TTL with a small electronic pcb

Francesco Fazzolari

[Andy58]

In my application we have three absolute SSI encoders and we determined it was much easier to purchase the encoders with CANOpen features and the 9881 CANOpen module. This seems to work fine and was fairly simple to implement.

[CoastalLabVIEWER]

We've connected our probe to an R-Series card using the library linked here https://decibel.ni.com/content/docs/DOC-1095

We are giving the probe a clock signal and we can see it is responding but the data lines coming back aren't as nice as I'd like to see.  On data line negative edge transitions there appears to be ringing/overshooting followed by a slow decay to the low level I expect (it mirrors this behavior on positive edges).  However, with my 1GHz 5MS/s scope it appears that the logic level is established with plenty of time for us to sample on the FPGA side to detect a solid "bit" but that doesn't appear to be the case as the readout on the FPGA VI isn't stable.  It isn't super erratic, that is, multiple 1s together and multiple 0s together usually have the middle bits always get read correctly, which tells me the transitions are what's problematic.

We even tried delaying when we sample the bit to a little bit later to allow the signal to settle more and it doesn't seem to make a huge difference.  We've slowed the clock rate down to the 50Khz range, our cable length is about 10 ft of twisted pair connected via a little terminal block to another 5ft of twisted pair. 

The example in the link and the datasheet for our probe http://www.mtssensors.com/fileadmin/media/pdfs/R_Series_RP_RH_SSI.pdf

shows some termination resistors and optocouplers.  Would just the resisotors help?  

Is there something else going on in the FPGA that could improve things (sampling the line for more time and taking a median of the samples

Also, I'm not quite certain how to mate up the differential data lines from the probe to what are essentially single ended lines on the card (or does would my theoretical termination/optocoupler circuit take care of this for me?)  In lieu of the termination circuit should I wire to two seperate I/O  and...just ensure that what I read are complements of each other?

[CoastalLabVIEWER]

We connected a 100 ohm 1/4w resistor in series with the data lines coming from the probe and it fixed the ugliness in the signal we we're seeing on our scope.  We we're able to run the clock as fast as 1MHz  (we didn't try any faster) without any noticeable hiccups from the probe.

[Philip_Ehlers]

Hi

One of my clients are also looking at interfacing to the same sensor but with a cRIO. I assume the clock and data signals were all TTL voltage signals taking that you used the R series card with bidirectional 0-5V DIO. Did you do anything other than the resistors to convert the signals before it went into the NI R-Series card?