How to do buffered counting with pause trigger

[LCHEN5154]

I have problem to configure a buffered counting with pause trigger on a PCIe-6320.

It seems the the buffered counting doesn't direct support a pause trigger. So in the test vi (buffered_count_pause.vi,see attachment)  the True case in the case structure will not work.

I also have a look of example countdigevevents_cont_pause.vi but this is also not what I need. In this example you generated sample clock has a fix frequency but I need the sample clock to be my input digital signals.

I can also put my question like this: How to trigger the start/stop of a buffered counting?

thank you.

Lixin

[stilly32]

Hi Lixin,

The true case works as expected for me on an X Series - I used a 100Hz clock (from another counter) and just a static digital line for the pause trigger. When the pause trigger is low, the count doesn't increment, but when the pause trigger is high the count does increment. This is as described in the pause trigger section in the X Series Manual.  Regardless, I still get samples latched in on every edge of the sample clock - it sounds like this is what you are trying to gate.  Do you want the count to still increment while the sample clock is gated?

Gating a sample clock is more challenging. If you're not using one of your other timing engines, you could set up a dummy AI/DI/DO task, set it to use an external clock, pause trigger that sample clock, and use that sample clock as the sample clock for the counter. Would something like this work?

I haven't had a chance to test this, but I've attached an example that may do what you need.

Hope this helps,

Andrew S 

Message Edited by stilly32 on 06-17-2010 12:29 PM

[LCHEN5154]

Thanks, Andrew.

The true case now work for me too. The problem is only the counter gated not the sample clock. I mean when you have 100 sample clock cycles during the pause trigger low, the counter still transfer 100 times but the same number to the buffer. This somehow confused me in the first test.

It seems that I need gated sample clock as you suggested. I will test that example. thanks again.

Lixin