inverse sine FPGA

[Betty Boop]

I’m implementing inverse sine inside the FPGA VI. To do that, I use lookup table/LUT. I found the attached VI. I’m just wondering if there’s a way that I could be the one to set the input values in the LUT? In the attached VI, the input value is between 0-1023 which is the ‘address’. Is there a way that I could customize LUT for the input value (i.e. input values could be: -1, 0.8, 0.6.... not necessarily the address which is 0,1,...1023)? It’s because I’m having a hard time utilizing the attached VI in mapping the input and output to its true values (i.e. -1 to 1 for input, -pi/2 to pi/2 for output). 😞  Thank you very much for your time! 🙂

[Betty Boop]

Hi! 😄 It's okay. I've already devised a way 😄 Thanks anyway! 😄

[Dragis]

It would be great if you could provide the solution you came up with, just to complete the thread.

Not knowing what you did, I would say this is a case where you want to take a fixed point value between [ -1 .. 1 ) at the boundary of your node and return a fixed point value in the range [ -pi .. pi ). Inside your VI, you would reinterpret the fixed point input bits to an integer for the address. This would make it easy for you to change your VI to accept more bits and provide interpolation in the future if it's needed.

[Dragis]

Forgot to attach this above.