Confusion regarding FPGA deployment

[Daklu]

I have the attached fpga code that works as intended... most of the time.  (Open the png in a new browser window to view it.)  Sometimes I'll start up an rt vi written to interact with the fpga vi and the fpga vi just doesn't respond.  Specifically, setting the value of the Start button from the rt side doesn't do anything.  I suspect it's something I'm doing wrong rather than a bug in Labview.  It's apparent the deployment relationship between fpga and rt code doesn't work the way I think it works, but I'm not sure where the model I've mentally created differs from what it really does.

Questions:

1.  I've written the fpga vi with the idea that it runs continuously and the rt code can connect to it dynamically.  My intent is to load the fpga vi onto the crio, and have different rt vis interacting with it depending on what I need.  We're still in the R&D phase, so when I need to use a different rt vi I stop the previous one and click the run button in the new one and it gets deployed to the crio.  Sometimes this works fine, other times the fpga Start button doesn't seem to be working and I'm stuck in Standby mode.  Is this kind of dynamic connection a valid way to use fpga vis?

2.  The fpga vi is written so the fpga led on the crio flashes anytime it is running.  Sometimes when I stop the rt vi the led stops flashing, indicating the fpga vi was stopped.  I don't understand why this is happening.

3.  The Open FPGA Reference vi has three different linking options.  You can link to the build spec, the vi, or the bitfile.  It's not clear to me exactly how, or even if, these options change the runtime behavior of the vi.  Do I need to write my code differently depending on which of those three options I select, or are they options designed to allow developers to use the edit-time workflow that suits them best?  (i.e. If I link to a build spec, I can change the top level vi in the build spec, whereas if I link directly to a vi I need to change the Open FPGA Reference configuration--a source code change.)

4.  I've read that the Open FPGA Reference vi includes the bitfile in its saved data, and the bitfile is deployed to the fpga when that vi executes.  Does that happen regardless of which of the 3 linking options you select?

5.  If 4 is true, that implies there is no way to start an rt vi that interacts with an fpga vi that is already running, since the Open FPGA Reference vi will overwrite the fpga code currently executing.  Is that correct?

6.  There are several places where one can choose to "Run FPGA vi when loaded."  The build spec, the Open FPGA Ref configuration, and the fgpa vi's properties ("Run when opened" option) are three I can think of off the top of my head.  When those setting conflict, how do I know which setting will take precedence?

7.  How do the reentrancy options on a top level fpga vi affect it?  Help files mention rt vis, but not fpga vis.  Intuitively it doesn't seem like it should do anything since the vi is only being called once.

I have lots of other questions too, but they're somewhat dependent on the answers to these questions, so I'll stop for now.  🙂

TIA,

Dave

[Edit - I'm using a 9074 crio.]

[Daklu]

Cross-posted to LAVA.

[dwisti]

I remember long ago (Labview 8.5) having a issue similar. I had loop in the beginning of some FPGA code for acknowledging calibration constants were loaded.  That code did not have any wait function like your start loop.  Try adding a small wait to your loop and see if that helps.