I'm currently using Veristand to generate analog signals using a PXI target and a 7831R FPGA board.
I created a new workspace and used example sinewave(.dll) model to generate my signal. The output of the model is then linked to AO0 of FPGA device.
I noticed that the signal generate starts as soon as the system configuration is deployed and do not stop when stoping the workspace.
One solution to avoid the system generating signal when system is deployed is to set the model initial values to 0.
But how to stop the signal generation when exiting the workspace ? is there any better solution than modifying the initial values to avoid the system generating signals before running the workspace ?
Do you want the VeriStand Engine to stop running completely when you disconnect the Workspace? If you do want the VeriStand Engine to continue running on the target when the Workspace disconnects, what should it do if it no longer drives the analog output using the model value?
There are a number of ways to accomplish this, but I'd like to learn more about what you want to do first.
In my opinion, VeriStand engine could continue running on the target when the Workspace disconnects, but signal generation/acquisition should be stopped. Indeed, most final users do not understand that a program can continue running without any HMI running.
I guess that a custom device could disable signal generation on workspace disconnection, but is there any way to do it without creating such custom device ?
In this case your model is doing signal generation. But in the case where a model is performing a control algorithm, it might be very bad if the model would ever stop running simply because the Workspace disconnects.
In your case there are various ways to set up your VeriStand Engine to stop or disable a model when the Workspace disconnects.
Here is one idea: