How to use simulink model input/output bus in Veristand

[Smolet]

Hi,

i have a simulink model that i would like to test with VeriStand. This model has several inputs and outputs, and this are custom defined buses.

If i import mdl file of this model, Veristand did not recognize input and output buses at all

if i compile my model for Veristand Target, Veristand recognize the inputs and outputs but no as buses.

Some  ideas how i can use my input/output buses?

thank you!

[Jarrod_S.]

This is a known limitation of the VeriStand code generation process. VeriStand will currently interpet a bus signal as an array of values, one value for each element in the bus.

A workaround is to create a top-level model wrapper with individual model inports and outports that packs these into the inports bus, calls the sub-model, then unpacks them from the outports bus.

[Smolet]

thank you!

the workaround works!