Hi,
I have tried to compile the USRP E312 FPGA code (from usrp fpga github repository) only for DUC and processing system IP(ZYNQ PS) using Vivado GUI in windows But i am facing issues in resource utilization, there is an overshoot in the usage of BRAMs(110%) for xc7z020clg484-1. But when i compiled the same code(For DUC and processing system only from usrp fpga github repository) using your command line instructions. The Bitfile generated successfully.
How to resolve this issue?
Error -
[Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 408 of such cell types but only 280 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
Thanks in advance.
