Not all STIL patterns are created equal

[HauLam]

When DFT tools generate bus members as individual pins in STIL syntax, it can cause problems downstream when the tester is trying reconcile signal names.  For example:

Signals {

   "DM_DATA[31]" InOut;

   "DM_DATA[30]" InOut;

...

This is usually seen in VTRAN generated STIL files.  That's why recipient of these STIL files always have to debug the STIL files before going further with it.

TSSI's TD-ScanPRO has a "detect bus" mode to automatically fix this "sloppy" syntax.