03-23-2007 08:44 AM
03-26-2007 12:17 PM - edited 03-26-2007 12:17 PM
The PLL circuitry divides both the VCXO and the reference clock down to 1 MHz. A phase comparator then compares the two 1 MHz signals and sends out an error signal. This error signal is filtered and sent to the control pin of the VCXO whose frequency gets adjusted. To achieve phase-locked looping correctly, the external reference clock must be a multiple of 1 MHz and should have a frequency error of no more than ±50 ppm. The REF IN connector handles frequencies from 3 MHz to 20 MHz and amplitudes from 250 mVpk-pk to 5 Vpk-pk. Therefore, for your case, you can probably use PLL with a multiple of 1 MHz signal, like 13MHz or 14Mhz.
The following figure shows the block diagram for the NI 5404 device PLL circuit.
Message Edited by Raajit L on 03-26-2007 12:20 PM
03-26-2007 10:48 PM
03-27-2007 12:30 AM
03-28-2007 04:44 PM
03-28-2007 11:35 PM