Xilinks Compilation Error

[gbaguma]

Hello guys,

I Recently experienced a power outage when i was compiling FPGA VIs. Now every time i compile code

the VI server generates an error when it reaches the stage of Generating the programming file. i have made an extract from

both the xilinks log and the xillinks std error log. the contents are shown below.  I tried reinstalling the modules for xillinks and FPGA, it did not work.

i even reinstalled the Crio firmware, this did not also work and i dont know how to run theproject set top command for setting the. Please help me in this issue.

This information henceforth is from the log files

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

### Bitgen ###Started : "Generate Programming File".INFO:Bitgen:40 - Replacing "Pullnone" with "PullUp" for option "HswapenPin".    Most commonly, bitgen has determined and will use a specific value instead of   the generic command-line value of "Auto".  Alternately, this message appears   if the same option is specified multiple times on the command-line.  In this   case, the option listed last will be used.INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle".  Most   commonly, bitgen has determined and will use a specific value instead of the   generic command-line value of "Auto".  Alternately, this message appears if   the same option is specified multiple times on the command-line.  In this   case, the option listed last will be used.WARNING:PhysDesignRules:367 - The signal <temp_miso_IBUF> is incomplete. The   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <mIoAddr<0>_IBUF> is incomplete. The   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <mIoAddr<1>_IBUF> is incomplete. The   signal does not drive any load pins in the design.WARNING:Bitgen:26 - Bitgen only supports DRC but not bitstream generation on   this device.  This condition can occur if there are problems obtaining a   license to run bitgen or if the design targets a device which is Early   Access.Process "Generate Programming File" failed

-----------------from the xilinks error log--------------------
### PlanAhead ###
### XstSynthesis ###INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.   Please set the new top explicitly by running the "project set top" command.   To re-calculate the new top automatically, set the "Auto Implementation Top"   property to true.INFO:TclTasksC:1850 - process run : Synthesize - XST is done.
### Translate ###INFO:TclTasksC:1850 - process run : Translate is done.ERROR:TclTasksC:process_077: Failed to complete. Please inspect the log and report files.false    while executing"process run "Translate""    (file "C:\NIFPGA\jobs\ia5e3vS_DL3da4H\translate.tcl" line 9)INFO:TclTasksC:1850 - process run : Translate is done.
### Map ###INFO:TclTasksC:1786 - Property "Map Effort Level" is currently disabled, due to   the value of another property. The value has been set but will not be used.INFO:TclTasksC:1850 - process run : Map is done.INFO:TclTasksC:1850 - process run : Generate Post-Map Static Timing is done.
### Par ###INFO:TclTasksC:1850 - process run : Place & Route is done.INFO:TclTasksC:1850 - process run : Generate Post-Place & Route Static Timing is   done.
### Bitgen ###INFO:TclTasksC:1786 - Property "Create Mask File" is currently disabled, due to   the value of another property. The value has been set but will not be used.INFO:TclTasksC:1850 - process run : Generate Programming File is done.ERROR:TclTasksC:process_077: Failed to complete. Please inspect the log and report files.false    while executing"process run "Generate Programming File""    (file "C:\NIFPGA\jobs\ia5e3vS_DL3da4H\createBitFile.tcl" line 17)

[Thør]

Does this happen when you try to compile any code, or is it just a certain program that causes this?  Does the same error come up if you try compiling a very simple VI?  Perhaps try this with something as simple as taking a logical AND of two inputs.

I'd also like to know, which version of LabVIEW are you using and which version of Xilinx Tools?

[gbaguma]

yes, this happens for every piece of code i try to compile, even thecode that would prevoiusly compile. Am using the NI 3-6.0 Rio driver and Labview 10.0 (32 bit). The xillinks software is version 11.5.

[Thør]

It's possible that using NI-RIO 3.6 is causing this error.   According to this KnowledgeBase article, NI-RIO 3.6 requires LabVIEW 2010 SP1 (10.0.1).  If you're using LabVIEW 2010 (10.0), then the recommended version of this driver is 3.5.1.  If you'd like to test this, you can download 3.5.1 here.  You will need to first uninstall NI-RIO 3.6, and then install 3.5.1.

[Thør]

I'm not sure if you're still seeing this issue or not, but I'm also interested in a couple of other things:

1) What target are you compiling this for?  If you have the model number of the cRIO chassis, that would be great.

2) Does this error occur even if you try compiling for a different target?  You could try creating a new target in your project and see if the same error crops up.