02-08-2011 04:08 AM
Hello,
I'm using the Reference Example for Streaming Data from FPGA to cRIO to Windows found on http://zone.ni.com/devzone/cda/epd/p/id/5919 on a cRIO 9074.
It works fine, the only problem is that after start-up, it takes about 18 seconds before any data is transmitted over TCP. So unless using a huge RT FIFO, some data is lost. After these initial 18 seconds it works perfectly. I have tried changing the different time-outs and FIFO sizes, but nothing seems to have an impact.
Does anyone else have this problem (and maybe even have a solution!)?
Thanks
02-09-2011 02:56 AM
Hello,
Thank you for posting on National Instruments forum's.
The VI that you use is FPGA>Main?
Brice S.
National Instruments France
02-09-2011 04:01 AM
Yes, it is main.vi.I just added my inputs to it, and it runs properly at 800 ticks.
02-09-2011 04:16 AM
Hi,
Have you tried using a loop timing? But it will have removed the tick count of the previous loop.
Brice S.
National Instruments France
02-09-2011 04:55 AM
Hello,
The FPGA uses loop timing indeed. You will find the project in attachment.
Thank you for your help.