I am using the NI-9401 module in the NI cRIO-9073 chassis, and am attempting to create a 20kHz PWM signal to drive a motor control circuit. Generating the PWM signal works. For some reason the voltage offset changes as the duty cycle is increased. This is less effective for the motor driver, as you can imagine.
The code I am using comes from the Example finder, for PWM generation on an FPGA, and is attached.
I thought this was working previously but may have used the PWM output of the NI-9505 instead to test my circuit. This would be overkill for me to do this as a permanent fix.
The problem can be summarised as such: with an increase in the duty cycle the voltage base-line (offset) of the output signal shifts into the negative (according to dCRO) or down. The Vpp of the signal is correct and does not change. From 0 ticks to the maximum of 2000 ticks (duty cycle IN), the voltage offset shift is such that at 100% duty the full voltage level is at 0V.
Any ideas as to why this voltage offset shift is happening ??
