Timing violation in 7965R with 5761

irad · ‎11-14-2012

Hello,

I am using a FLEXRIO card (7965R) and an ADC IO module (5761) to signal processing in real time
at 200 MHz. The fpga vi fails to compile due to a timing violation. The project file and fpga vi (both in Labview 2012)
are attached.

The main single cycle timed loop is controlled by the IO module clock, which is set to compile at 200MHz.
The 5761 clip node is configured to provide a single sample in each clock cycle. ADC samples are processed by an IP
module that is configured by an ngc netlist generated in Xilinx System Generator. Processed data is sent to the host
through a DMA FIFO, which is placed in slower single cycle timed loop running at 105 MHz. The IO module clock timed loop
is connected with the 105 MHz timed loop through a target scoped fifo.

An obvious block to blame for the timing failure would be the IP block. However, I believe there is enough slack in that
block from what I have seen in System Generator and ISE tools. The IP block timing constraint produced by System
Generator is labelled TS_clk_dcd7bca7. The clock period for that constraint is 5ns. The Xilinx report in Labview FPGA
(place and route section) shows that there is a slack of 1.364 ns.

The single failing time constraint is shown below

It only fails by 39 ps. It appears that the clock frequency is 250 MHz. I don't know where it comes from. The sampling frequency is set to 200 MHz.

I know that compilation would probably become easier if I switched to the multicycle CLIP node where two samples are delivered in each clock period,
so that the clock frequency can be twice as low. In that case however, I would need to transfer samples to another clock domain, which runs slightly
faster than 200MHz. This means that I would have to use a clock enable signal for every block in the processing chain because some clock cycles
would not carry valid ADC samples. I am trying to avoid having to add a clock enable signal, if possible.

I'd like to hear if there are any ideas on how to compile my current labview fpga vi. I've tried adding some registers aroung the IP block but that didn' t
help. Any feedback including links to articles is welcome.

Best regards,

Ivan

ColdenR · ‎11-15-2012

Hello irad,

The 5761 is a 250MS/s ADC IO module, so its IO Module clock will run at 250MHz. It also has to sample using a clock on the 5761. You can't import clocks from the FPGA (7965R). If you open up the help file for the 5761 Single Sample CLIP (search for "5761" in LabVIEW help), it shows that you can choose from 5 different clock sources for your sample clock. You can use the internal clock (which is 250MHz, and is the default), you can synchronize with an external clock through PLL, you can use an external clock, and you can lock to or use the IoModSyncClock, which is only available for some FlexRIO cards.

So basically, your code is set to run at 250MHz because you're using IO Module Clock 0 to time the loop (which is correct - if you did anything else it wouldn't work correctly).

What I would suggest is to FIFO the data out into your target-scoped FIFO right away. Then do the IP Block processing in a slower loop. Another option that should work would be adding feedback nodes on both outputs of the AI Data and on the output of the IP block. Here's a screenshot showing what I mean:

I would also say that you probably should put your sample clock configuration IO node in a separate independant loop. There are examples in the example finder (if you search for 5761) that show how to set up some basic acquisitions and do clock selections. See "NI 5761 - Clock Select.lvproj" for example.

Colden

irad · ‎11-15-2012

Hi Colden,

Thanks for your reply. Adding feedback nodes often helps, but it didn't help in this case unfortunately. I actually tried that before I posted my question on the forum.

I still have to try placing the configuration node in a separate timed loop. I have to see first what's wrong with my Labview help. There are no matches when I type "5761".

I am confused about the IO module clock. You are saying that the failing timing constraint is related to that clock because it set to run at 250 MHz. What about setting up the IO module clock to compile for a single frequency? When I right click on the IO module clock 0 in the project window and select 'Properties', I can see the option 'Compile for single frequency', which I set to 200 MHz. This worked as I expected in the past.

If the IO module clock really runs at 250 MHz, the whole structure of my VI doesn't make sense because the IP block runs at 200 MHz and expects to receive inputs at that rate.

ColdenR · ‎11-16-2012

Hello irad,

You can also download the FlexRIO help from here:

http://digital.ni.com/manuals.nsf/websearch/D4BDAC1E4FED4EEC862577310057362A

And the user guide and specs for the 5761 are good as well:

http://digital.ni.com/manuals.nsf/websearch/E74018314786C9C7862577270079CB91

The "Compile for single frequency" setting is for how the FPGA compiles the timing for the clock. It should be set to 250MHz if you're using the base clock. If you use an external clock of if you use the IoModSyncClock then you should change that compile setting to match your expected clock speed. It doesn't determine the speed of the clock, it just modifies how the FPGA compiles.

I would say though that you probably want to back up a little bit and look at the example for the 5761, specifically the single-sample CLIP example example. (Just search for 5761 in the example finder). In general the 7965R is going to have trouble compiling at 250MHz, so you should minimize what you have running at 250MHz as much as possible. You should pass the data from your 250MHz acquisition loop into a 200MHz loop for your IP block, and then possibly into another loop for transmitting up to the host.

Also, from speaking with people from R&D, the 7966R would be a better match for the 250MHz speed you're looking at. If you have access to a 7966R I would recommend that instead.

Colden

irad · ‎11-18-2012

Hi Colden,

Actually I do use the IOModSyncClk generated by the 6674T timing module. That's why I set 'compile to single frequency' to 200MHz. So, I don't need to have

anything running at 250 MHz. And yet, I have a failing timing constraint that appears to have a period of 4ns. Anyway, I'll see what happens when I place the IO module configuration node in a separate timed loop.

Ivan

ColdenR · ‎11-19-2012

Hello irad,

If you are using the IOModSyncClk, are you wiring a "4" to your sample clock select? Also, after selecting the sample clock, do you commit the sample clock using the "Sample Clock Commit" input? The example I referenced earlier ("NI 5761 - Clock Select.lvproj") shows how to do that.

Putting the IO module configuration in a separate loop might not resolve the issue. I would try putting your IP block in a separate loop and just use a target-scoped FIFO for data transfer. That should be able to compile fine, since we know that the data acquisition will run at 250MHz or 200MHz, and you've already verified that your IP Block compiles at 200MHz.

Colden

irad · ‎11-19-2012

Hi Colden,

Yes, I set the clock select input to 4, and I also use the clock commit input in the same way as in "Clock Select.lvproj". That is on the host side though. What I am trying

to find out is whether there is a way of setting up the project so that it doesn't require the adc loop in the fpga to be able to run at 250 MHz. That would make a big difference because there is a big difference between 200 and 250 MHz. I thought that setting the 'compile for single frequency' option of the IO module clock 0 to 200 MHz would take care of it, but that doesn't seem to be the case. Maybe hardwiring the clock select input to a constant with a value of 4 in the fpga vi would do the trick?

Eventually, I may have to take out the IP block, put it in a separate single cycle timed loop,and connect it with the adc loop through a target-scoped fifo as you mentioned. However, the two loops would be asynchronous, which means that I would have to add a clock enable signal in the IP block that ensures that processes in the IP block run only when there is a valid sample. It is not a big coding effort, but the clock enable signal would have a high fanout. This could create another compilation problem especially down the road as the IP block grows. That's why I am still trying to compile the project in the current form.

Ivan

ColdenR · ‎11-20-2012

Hello irad,

As long as you have selected the clock correctly, your loop should run at at the speed that your IoModSync clock is running. Setting the FPGA to compile for 200MHz doesn't determine what speed the clock actually runs, it just determines how the FPGA VI gets compiled. Since you're using a clock that is external to the FPGA, you are relying on that clock to run at the frequency you want.

I believe the issue we're running into here is that the speed grade of the PXIe-7965R is relatively slow. The PXIe-7966R (http://sine.ni.com/nips/cds/view/p/lang/en/nid/210272) is the same price and has the same stats, except that it has a faster speed grade.

Also, the target-scoped FIFO has a "Timed out?" output, which will let you know whether or not the data is valid. On "Write" the timeout indicates if the FIFO was full and the FPGA was unable to write. On "Read" the timeout indicates if the FIFO was empty. So you can use that indicator to determine whether or not your data going into your IP block is valid.

Colden

Real-Time Measurement and Control

Timing violation in 7965R with 5761

Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761

Re: Timing violation in 7965R with 5761