Problem reading NI-9401 DI

[golubovski]

Hello,

I am playing with a cRIO-9073 with NI-9401, NI-9239 and NI-9263 (slots 1, 2 and 3). Still in RT (Scan Engine). I simply cannot read a digital input from the 9401. I am streaming a TTL pulse trian to DIO0 (all DIO configured as INPUT). The Distributed System Manager sees the TRUE/FALSE toggling but I cannot make it read it in neither my Host VI, nor in my RT VI any possible way.

Can somebody send me a working example for Scan mode?

Thanks in advance,

[golubovski]

Correction - the RT VI can capture the TTL toggle, but I can't pass changes to the Host VI.

[KHartley]

Hey Golubovski,

So to get values to be passed to and from your host VI and RT vi you can use network shared variables or network streams. 

Network Shared Variables

http://zone.ni.com/devzone/cda/tut/p/id/12176

Network Streams

http://zone.ni.com/devzone/cda/tut/p/id/12267

Here's a tutorial that goes over the benefits of each networking method. 

http://zone.ni.com/devzone/cda/tut/p/id/12079

Depending on how fast the changes are occuring you may need to try out several different methods.

Also I just wanted to let you know that the scan engine runs at 1000Hz so definitely make sure you're not changing the values too quickly. To get faster sampling you'll have to modify the FPGA code, which is possible through LabVIEW. 

You should be able to run the same VI on the host computer and read the values from modules but there is a delay reading the data across the network so you may not see every value. You may find it to be a better option to pass back an array of 100 samples or so to cut down on the cost of connecting each time. 

[golubovski]

Hi Kyle,

I am so busy until 20 Mar that I just logged in to check on replies and respond. I have downloaded the tutorials and they are helpful and general so one needs to recognize its situation in the written scenarios in order to make use of them. What I need I guess is practical experience from others (like you). My play with the cRIO is to achieve some knowledge on how to use AIO, DIO and CTR on one hand, and more importantly how to propagate waveforms, statuses (numbers and booleans) and processed data types from FPGA.vi to/via RT.vi to Host.vi and back! Before going into the FPGA mode I wanted to get familiar with the RT mode (Scan Engine and controller) so this is why I still tackle with the Scan Engine :))) Please address the following 2 topics:

1. Passing boolean status from RT.vi to Host.vi

The observed process is a TTL 50:50 train at 1Hz, so the 1kHz Scan Engine should catch both levels ~500 times a sec. The RT.vi panel indicator works well. I tried to pass the DI0 variable (connected to the TTL source) exactly like the Stop status from the higher priority loop in the RT.vi (single process RT FIFO-ed boolean shared variable) to its lower priority network-dispatching loop which passes on that status via a network-shared variable to the Host.vi. And this does not seem to work regardless to RT FIFOs...!?

2. Communication principles according to your experience

Anyway, I'd like to adopt some unique and general communication (data passing) techniques on this general scenario:

a) FPGA domain

FPGA.vi acquires [INT32] waveforms (lets say up to 1Mhz), DIs (digital inputs) and decides for alarms (booleans or rarely INTegers).

It outputs DOs [BOOL] and AOs [INT32 ?].

b) RT domain

RT.vi requires from FPGA.vi [DBL/INT ?] waveforms, booleans (DIs & alarms). It loggs waveform and statuses on local file(s).

Host.vi requires from RT.vi [DBL] waveforms, booleans and FTP-ed files.

c) Host (PC) domain

Displays waveforms (AIs), DIOs, and accepts user swithching On/Off of FPGA's AOs and toggles FPGA's DOs On/Off.

How to pass waveforms (AIs) from FPGA.vi to RT.vi  - are Network Streams answer to all (sampling frequency) challenges?

How to pass waveforms from RT.vi to Host.vi - same or ...?

How to pass DIs from FPGA.vi, to RT.vi and from RT.vi to Host.vi - what is the general method that works for all frequencies?

How to pass waveforms (AOs) from Host.vi to RT.vi, and from RT.vi to FPGA.vi?

How to estimate/calculate RT FIFOs depth etc.?

Can you provide  dummy FPGA, RT and Host VIs depicting examples for everything above?

Givven that I am stucked in topic (1), would help me comprehend the whole concept.

Thank you again,

[KHartley]

Golubovski,

Here are a few example projects that should get you started the DIO is reading an input and relaying the information with another Network Shared Variable and the Host vi is reading that variable. There is a loop for generating the output since I didn't have another signal to read I used one of the ports as an output and pulsed a signal on it. There is another shared variable I use to stop then entire process. You can log the data by just dragging the line to the edge of the while loop and indexing an array which you can graph. 

Here's a getting started for Network Shared Variables.

http://zone.ni.com/devzone/cda/tut/p/id/4679

The second is a network streams project I created to test an issue from another customer, but it should who how to setup network streams. You'll need to change the ip address on the writer to whatever your targets ip address is and add your target to the project.

These, of course aren't everything you need but it is just a start. You'll gain alot out of messing with the program and working from any examples you find on our website or forum.

[golubovski]

Dear Kyle,

Thank you again for providing valuable examples. I will try and test them once I come back after 8 Mar :)))

Be in touch,