Real-Time Measurement and Control

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Is there a benchmark for reading and writing to an sbrio using the fpga read/write control?

Is there a benchmark for reading and writing to an sbrio using the fpga read/write control?

 

I am using a real-time vi (1 MHz timed loop) to poll a boolean indicator on my fpga vi (using fpga read control), and then when it comes true I want to write data out to the fpga vi using the fpga write control.

The fpga vi is running 40 MHz single cycle timed loop

 

We are seeing 3 to 6 msec, but need 1-2 usec.

 

Thanks,

 

Sean

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A list of Real-Time benchmarks can be found here:

 

You are looking for single-point real-time performance on CompactRIO/NI Single-Board RIO, which has been pulled out here.

 

"T1" is the benchmark that sounds the most applicable to your test scenario.  On the relatively high performance cRIO-9024 (800MHz processor relative to the 400MHz procesor on Single-Board RIO), that closed loop time is roughly 14us, which wouldn't meet your requirement.  On top of that, it is generally accepted that "T1" is a poor architecture for real applications (good for benchmarking relative performance between controllers, but not a good way to build a deployed applications.)  "T2b" is generally more applicable to a real application architecture, and it peaks out with closed loop control with RT/FPGA Read/Write in the loop around 20k (50us).  

 

I don't recommend trying to close the control loop with IO with your LabVIEW Real-Time VI.  For your target rates (1-2us), I would recommend moving your control logic directly to the FPGA, where your loop can reliably run at 40MHz (25ns).  If you check for errors on your 1MHz timed loop in RT on your existing code, you will find that it isn't actually running at 1MHz due to the FPGA write and read commands in the loop.

 

Cheers,

 

Spex
National Instruments

To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be has a 2x safety factor...
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Thank you. I would have thought that the Real-time compiler would have told me if it couldn't keep up. I am moving a lot of data, so I thought that I could feed it from the Real-time code, but I'll try moving everything to the FPGA.

 

Thanks again,

 

Sean

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The compiler cannot predict the real-time performance of the code.  That must be determined during execution.  If you are using a timed loop, the loop structure itself is time-aware.  There are extra input and output nodes that you can add to a timed loop to monitor the real-time performance of the loop, including events like "finished late?" and "Actual End" time to determine if your code is executing at your expected rate.

 

The LabVIEW help has a good overview of your options:  Timed Loop 

 

Cheers,

Spex
National Instruments

To the pessimist, the glass is half empty; to the optimist, the glass is half full; to the engineer, the glass is twice as big as it needs to be has a 2x safety factor...
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