How to write to FPGA

[tlin067]

Hi there,

I want to generate a MLS sequence in host code and pass it to a FPGA to store in RAM. As my chassis model is cRIO 9004 I cannot use host-target DMA FIFO's. I considered writing to a control array on the FPGA front panel but due to the large length of the sequence I wish to generate, this will use up too much space on the FPGA.

Instead I am trying to write the MLS sequence one point at a time to a control and then writing the value in the control to memory. I can't figure out how to do this. I think I am getting confused about how to control the timing so that one value is passed to memory everytime the control changes....

Thanks in advance!

[Charlie_P]

Hello tlin067,

You are absolutely correct to not want to use a large control array on your FPGA.

Have you tried the Read/Write Control VI to get the new values to the FPGA?  You can put this in a while loop with a comparison VI and Case Structure to only send the new values.  Alternatively, maybe you want to use an Event Structure to detect the change in value.  This choice will depend on the speed which your values change and your comfort coding each of the two methods.

[tlin067]

Yeah i thought of that but instead I thought it better to work with the timing as some iterations the value in the sequence may not change.... i.e the sequence may be 0 1 0 1 0 0 1 1 1 0 1 etc....

An event structure will that pick up a change in the control if the value displayed does not change? 

Thanks

Tom

[Christian_L]

You should use a handshaking mechansim to transfer the data from RT to the FPGA.

On the front panel of the FPGA VI you will have a numeric control for the value to load and a Boolean button (Latch when pressed) to tell the FPGA to load the value. As an option you can also add a separate numeric control to specify the memory address to which you want to store the value. As an alternative you can start at address 0 and increment the address by one every time a value is loaded. In this case you may want to add a Boolean to reset the address back to zero.

In the FPGA code, check the Load Boolean and when it is pressed, take the value from the numeric control and write it to the FPGA memory (block). After writing the value to memory, increment the register address if you do not have an explicit address control. Wait for the next value.

FYI, the event structure is not supported on the FPGA.

Message Edited by Christian L on 01-22-2009 02:18 PM

[tlin067]

Sorry does that mean it will only load into memory when I push the boolean control??? Sorry I'm a little confused!!!

[Christian_L]

Yes, that is correct. Pressing the Load button, or setting it to True from the host VI running on the processor in the cRIO controller, will load the current value in the numeric control into memory.

Typically you would not do this from the front panel of the FPGA VI interactively, but write the host VI to automate this process. It does make interactive testing of the FPGA a little difficult (or impossible), but that is the limitation. As you stated since you may have the same value repeated in the data stream that you want to load to the memory, you must have some way to tell the FPGA VI (the Load button) when the next value is ready to be loaded to memory.

Here's an example of a host VI that automates the downloading of the data to the FPGA and memory.

You do have the option to specify some default data for the memory block you are using, which you could use for interactive testing. This way the memory will have valid data for your application stored whenever the FPGA VI is started. You define the default data where you define the properties of the memory block.

Message Edited by Christian L on 01-23-2009 09:58 AM

[speleato]

As a note, I think that for this to work properly the FPGA code should reset the boolean to false after reading the data and the RT code should monitor the boolean and only write to it when it is in the false state. 

If you don't like the idea of polling syncronization it is also possible for the FPGA to raise an interrupt to indicate that it is done.

In a practial sense, it is unlikely that the RT code will overwrite the data before the FPGA has read it due to the relative rates at which the loops run, but it is critical that the FPGA reset the boolean otherwise it will continously read the same value. 

[tlin067]

Sorry the way I understood it was that you could not write directly to block memory inside the FPGA from the host code? One more note.... I have been told that having an array control on the fpga uses up RAM and not anyother of the resources of the fpga? Is this correct?

[Christian_L]

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tlin067 wrote:
Sorry the way I understood it was that you could not write directly to block memory inside the FPGA from the host code? One more note.... I have been told that having an array control on the fpga uses up RAM and not anyother of the resources of the fpga? Is this correct?

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Correct, you can not write directly to the block RAM on the FPGA from the host VI. Therefore you need to use a small bit of code, like the one I posted at the top, which will run on the FPGA and copy data from the FPGA VI front panel to the block memory whenever the Load button is pressed, or the Load button is set to True from the host VI.

Any data (arrays, scalars, clusters, etc.) on the front panel or on the diagram of an FPGA VI use up FPGA gates, not the block RAM on the FPGA. If you define large arrays on the front panel or on the diagram you can run out of FPGA gates (slices) very quickly. Therefore we recommend that you do not directly use large arrays in your FPGA VI (diagram or front panel). If you need to store larger amounts of data on the FPGA, you can store such arrays using the block RAM that is part of the FPGA. Block RAM is separate from the FPGA gates and can only be used to store data (memory blocks and FIFOs). When the data is stored in the block RAM, you can access one or a few elements at a time. without keeping the whole array in your FPGA VI diagram.

Using the technique described above you can copy a large array of data from the host VI to the block RAM on the FPGA, without ever keeping more than one element of the array in the FPGA VI front panel diagram. Therefore this method is very efficient in the FPGA gate usage (number of slices). The data array is stored in the block RAM, not the FPGA gates on the FPGA.

[xcx]

Maybe don't understand, but MLS (even very long) is easy to implement in FPGA logic (very short vhdl code)

What is the point in generating it elswhere and coping to FPGA?