Generating a sine wave of exactly 60.0000 Hz with 0.0001 Hz frequency control on cRIO9035 (FPGA mode) with NI 9263

[Adheesh]

Hello, 

I have a cRIO 9035 and a NI 9263 Analog Out module which is capable of generating 100 k samples/sec.

With a top-level clock of 40 MHz, and the sine generation block, I am unable to a perfect 60 Hz signal. It either gives me 59.995 or 60.005 which is not good enough for my application.

I tried with a custom look up table as well and still am not able to get a fine control over the frequency of the generated sine wave.

I am wondering if at all it is possible to get such level of control over my generated wave's frequency, and if so, what approach I should follow?

I am attaching VIs of the two approaches that I have tried so far. 

Thanks

[MarkCG]

(1/60 Hz) / 25 ns = 666,666.66666  , not an integer, so you will not be able to do it with the 25 ns fpga tick from the 40 MHz clock, you have to create a derived clock and run a single cycle time off it. 60 Mhz would work. YOu may be able to put your analog output node directly in the SCTL or if that doesn't work you could then use this single cycle timed loop and the "occurrence" functions to trigger your analog output generation in a second normal loop containing your analog IO node .

[nanocyte]

You should consider this design that accumulates any phase offsets over time.

In my case the while loop takes 2.8us (calculated from "loop rate") to run so if I increment by 0.000336 each iteration, it will take 5953 iteration to go from -1 to 1.000208. 5953*2.8us = 16.6ms which is close to 60hz.  The integer max is 1.0 so the remaining 0.0002082 wraps to the next cycle as a "phase offset" which makes the sine wave 60.0000Hz

[Adheesh]

Hi Mark,

Thanks for your comments. The analog output node does not work inside the SCTL. I tried using the occurance functions and ran into the following error (picture attached). Am I making some obvious mistake in the way occurance functions are to be used?

[James_McN]

There are two sides to this:

Software

As has been suggested you need to check that your sample rate and LUT match. I would use loop timing to control the sample rate explicitly and make sure it is a multiple of the base clock ticks that you have generated your LUT for and you need to ensure you have an integer number of ticks per cycle to make life easier. As you have discovered you cannot use this module in a SCTL so instead you would have to change the top level clock for the design. Before you worry about this - read on.

Hardware

I'm not sure this is actually possible with the hardware but I would love someone to check my maths.

This all depends on the timing accuracy. 0.0001Hz error on 60Hz is 1.66ppm by my calculations.

However the clocks on the cRIO are only accurate to 40ppm at 25 degC or 200ppm overall. What does that mean? When you assume 1 tick is 25ns, at 25 deg it could actually be 25.001ns.

This would lead to an error of 0.0024Hz. So with the onboard clocks, there is no way to guarantee that level of error. The options to do that become complicated or impossible. (I'm guessing you could use an external source and PLL to it as a better reference, but I'm not sure that the cRIO has the IO for that)